# US 5,596,738 A · Peripheral device control system using changeable firmware in a single flash memory > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,596,738 A - Document ID: US5596738A - Status: Granted - Kind: A - Application number: 08/421,462 - Filed: 1995-04-12 - Granted: 1997-01-21 - Earliest claimed: 1992-01-31 - Assignees: TEAC Corporation; DZU Corporation - Inventors: Steven M. Pope - Web page: https://patentgrep.com/patent/US5596738A ## CPC - G06F 8/60: Software deployment - G06F 9/24: Loading of the microprogram - G06F 9/4401: Bootstrapping (security arrangements therefor G06F21/57) - G06F: ELECTRIC DIGITAL DATA PROCESSING (computer systems based on specific computational models G06N) ## Abstract A peripheral device control system includes a single flash memory having a changeable portion for storing firmware for controlling the peripheral device and a preprogrammed portion containing control code. When it is desired to modify the changeable firmware, the control code is read from the flash memory to a storage area in the using system and is used to control the loading of the modified firmware in the flash memory. ## Claims ### Claim 1 A peripheral device controller disposed on a printed circuit board located in a housing comprising: a single flash memory chip disposed on the printed circuit board, the single flash memory chip including a preprogrammed portion having recorded control information stored therein and a changeable portion to receive and transmit changeable information; a digital signal processor disposed on the printed circuit board, the digital signal processor including a memory store the memory store receiving said recorded control information from said preprogrammed portion of said single flash memory chip and storing said recorded control information in said memory store; said digital signal processor executing the recorded control information from the memory store during firmware changes, and said digital signal processor transmitting said recorded control information back to the preprogrammed portion of said flash memory chip upon completion of said firmware changes. ### Claim 2 (depends on 1) A system in accordance with claim 1 wherein old information has been recorded in the changeable portion of the single flash memory chip and new information is to be recorded in said changeable portion further comprising: means for comparing the old information recorded in said changeable portion with said new information prior to recording said new information in said changeable portion. ### Claim 3 (depends on 1) A system in accordance with claim 1 in which said changeable portion of said flash memory chip is divided into units, and means for supplying new information for recording in said changeable portion one unit at a time. ### Claim 4 (depends on 3) A system in accordance with claim 3 including means for determining whether said new information to be recorded includes data for recording in more than one of said units of said changeable portion of said flash memory chip. ### Claim 5 (depends on 4) A system in accordance with claim 4 including means for halting recording of said new information at an end of one of said units. ### Claim 6 (depends on 5) A system in accordance with claim 5 including means for resuming recording of said new information in a next unit adjacent to said one of said units. ### Claim 7 (depends on 1) A system in accordance with claim 1 in which said recording means and said reproducing means do not operate simultaneously on the recorded control information and the changeable information of said flash memory chip. ### Claim 8 A peripheral device controller disposed on a printed circuit board located in a housing comprising: a single flash memory chip disposed on the peripheral device controller, said single flash memory chip including a preprogrammed portion having recorded control information stored therein and a changeable portion to receive and transmit changeable information; a distal signal processor including a first store, said first store receiving and temporarily storing recorded control information from the preprogrammed portion of the flash memory chip; a second store disposed on said peripheral device controller, said second store temporarily storing the changeable information to be recorded in the changeable portion of the single flash memory chip; and a microprocessor responsive to said recorded control information in said first store, the microprocessor recording from said second store the information to be recorded in said changeable portion of said flash memory chip, the microprocessor transmitting the recorded control information back to the preprogrammed portion of the flash memory chip upon completion of the firmware changes. ### Claim 9 (depends on 8) A system in accordance with claim 8 wherein old information has been recorded in the changeable portion of the single flash memory chip and new information to be recorded in said changeable portion further comprising: means for comparing the old information recorded in said changeable portion with the new information prior to recording said new information in said changeable portion. ### Claim 10 (depends on 8) A system in accordance with claim 8 in which said changeable portion of said flash memory chip is divided into units, and means for supplying new information for recording in said changeable portion one unit at a time. ### Claim 11 (depends on 10) A system in accordance with claim 10 including means for determining whether said new information to be recorded includes data for recording in more than one of said units of said changeable portion of said flash memory chip. ### Claim 12 (depends on 11) A system in accordance with claim 11 including means for halting recording of said new information at an end of one of said units. ### Claim 13 (depends on 12) A system in accordance with claim 12 including means for resuming recording of said new information in a next unit adjacent to said one of said units. ### Claim 14 (depends on 8) A system in accordance with claim 8 in which said recording means and said reproducing means do not operate simultaneously on contents of said flash memory chip. ### Claim 15 A processor for controlling a peripheral, the processor disposed on a printed circuit board located in a housing containing the peripheral comprising: a single flash memory chip disposed on the printed circuit board, the single flash memory chip having a preprogrammed portion containing BOOT code and a changeable portion containing changeable firmware; a signal processor disposed on the processor, the signal processor having read alterable memory, the read alterable memory storing the BOOT code during firmware updates; a bus transferring the BOOT code from the single flash memory chip to the read alterable memory; the signal processor controlling writing of data to the changeable portion of said single flash memory chip by executing the BOOT code stored in the read alterable memory. ### Claim 16 A microprocessor disposed on a printed circuit board located in a housing containing a peripheral comprising: a single flash memory disposed on the printed circuit board, the single flash memory containing firmware data; said single flash memory having a preprogrammed portion containing BOOT control code and a changeable portion; a RAM disposed on the microprocessor, the RAM receiving BOOT control code, and the RAM storing the BOOT control code during firmware updates, the microprocessor loading said RAM with the BOOT control code, and said microprocessor executing said BOOT control code located in the RAM to write new firmware data to said changeable portion of said single flash memory. ### Claim 17 A method for modifying micro-code on a peripheral device controller disposed on a printed circuit board located in a housing containing a peripheral comprising: providing a single flash memory chip disposed on the printed circuit board; dividing said single flash memory chip into a BOOT code section and a changeable section; loading a RAM onboard said peripheral device controller with said BOOT code, the RAM storing said BOOT code during firmware updates; reprogramming the single flash memory chip with BOOT code located in said RAM, said BOOT code controlling writing of data to the changeable section of said single flash memory chip; providing modified firmware data; and executing said BOOT code from the RAM to write said modified firmware to said changeable portion of said single flash memory chip. ### Claim 18 (depends on 17) The method of claim 17 further comprising: comparing the changeable section with the modified firmware prior to writing to the single flash memory chip. ### Claim 19 (depends on 17) The method of claim 17 wherein the changeable portion is divided into units and further comprising: writing to said changeable portion one unit at a time. ### Claim 20 A method for modifying a page of firmware on a controller disposed on a circuit board located in a housing containing a peripheral comprising: providing a flash memory chip disposed on the circuit board; dividing said flash memory chip into a BOOT code section and a changeable section; locating the page of firmware in the changeable section of the flash memory chip; loading a RAM disposed on the controller with the page of firmware; executing a change or changes on the page of the firmware in the RAM to modify the firmware; and writing the modified firmware back to the changeable portion of said flash memory chip.