US 5,596,609 A · Parallel cascaded integrator-comb filter

Abstract

A high speed digital filter for use in digital interpolation and decimation provides a parallel processing implementation for integrator stages of a cascaded integrator-comb (CIC) filter. The parallel structure of the present invention is easily cascadeable since it allows subsequent integrator stages access to intermediate samples generated by preceding integrator stages. The parallel integrator structure may be implemented directly or may be reduced in complexity by removing redundant logic for use in decimator output sections or interpolator input sections. The parallel implementation of a CIC filter allows much higher sample rate filtering to be implemented with fewer standard CMOS logic devices than currently recognized implementations.

Claims14

Dependent claims

A cascadeable integrator for use in a digital filter which receives a series of data words each represented by a plurality of parallel data bits, the integrator for processing a predetermined number of the series of data words in parallel during each of a plurality of clock cycles, the integrator comprising:

a first layer, including at least one summing element and at least one delay element, for receiving the predetermined number of data words in parallel and generating a first sequence of parallel output data words in response thereto, the first sequence of parallel output data words being available to at least one subsequent layer;
and
at least one subsequent layer including at least one accumulator and at least one summing element, the at least one subsequent layer being connected to the first layer for generating a second sequence of parallel output data words, wherein each of the first sequence parallel output data words represents an integration of a unique sequence of previously received input data words so as to allow cascading of the integrator with subsequent parallel data word integrators.

A parallel integrator for use in a digital filter which receives a series of data words each including a plurality of parallel data bits and converts the series to a first sequence of parallel input data words, the integrator comprising:

a first layer for receiving the first sequence of parallel input data words and generating a second sequence of parallel data words, the first layer including a first summing element for generating a sum of two of the first sequence of parallel input data words, a multiplier for generating a product of the sum and a predetermined constant value, an accumulator for adding the product to previously generated products, and a delay element for providing a time delay to one of the first sequence parallel input data words so that the second sequence of parallel data words is received substantially simultaneously by at least one subsequent layer;
and
wherein the at least one subsequent layer is connected to the first layer for generating an output signal representing an integration of the previously received parallel input data words.

Dependencies are inferred from the claim text.

Parallel cascaded integrator-comb filter

Life of this patent

Parallel cascaded integrator-comb filter

Life of this patent

Abstract

Claims14