US 5,596,526 AGranted

Non-volatile memory system of multi-level transistor cells and methods using same

AssigneeLexar Microsystems, Inc.

InventorsMahmud Assar, Parviz Keshtbod

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Abstract

A multi-level NAND architecture non-volatile memory device reads and programs memory cells, each cell storing more than one bit of data, by comparing to a constant current level while selectively adjusting the gate voltage on the cell or cells being read or programmed. A plurality of read and write reference cells are provided each programmed to correspond to one each of the multi-level programming wherein during reading of the memory cells, the read reference cells provide the constant current level and during writing to the memory cells, the write reference cells provide the same. Furthermore, during a read operation, corresponding write reference cells are coupled to read reference cells to gauge the reading time associated with reading of memory cells.

Claims28

Dependent claims

A memory array of multi-level non-volatile single transistor cells, wherein each cell is configured to store more that a single data bit, the array comprising:

a plurality of groups, each group comprising a plurality of memory cells, each memory cell having a control gate, a floating gate and a channel formed between a source and a drain, wherein the memory cells for each of the groups are coupled with their respective channels in series;
a plurality of select transistors, wherein two of the select transistors are coupled for selecting each group;
a programming circuit for selectively programming each of the memory cells to a predetermined current level in accordance with one of N gate voltages by storing a predetermined charge onto each of the respective floating gates wherein each of the N threshold voltages is representative of a predetermined collection of data bits:
a plurality of N write reference cells, N write reference cells for each memory cell in a group, each of the N write reference cells corresponding to the N predetermined reference voltages;
and
a circuit for sequentially comparing a current through one of the memory cells to a current through each of the appropriate N write reference cells for storing a collection of data bits.

3 more elements

A method of programming a memory array of multi-level non-volatile single transistor cells, wherein each cell is configured to store more than a single data bit, the method comprising the steps of:

providing a plurality of groups, each group comprising a select transistor and a plurality of memory cells, each memory cell having a control gate, a floating gate and a channel formed between a source and a drain, wherein the memory cells for each of the groups are coupled with their respective channels in series;
selectively programming each of the memory cells to a predetermined current level by applying one of N gate voltages by storing a predetermined charge onto each of the respective floating gates wherein each of the N threshold voltages is representative of a predetermined collection of data bits;
reading the memory tells by sequentially comparing a current through the memory cells to a current through one each of said N read reference cell for determining a stored collection of data bits;
and
gauging reading time of the memory cells by reading one each of N corresponding write and read reference cells simultaneously with said reading of a corresponding memory cell thereby providing sufficient memory cell reading time.

2 more elements

A multi-level non-volatile memory system comprising:

(a) a memory array comprised of a plurality of memory blocks;
(b) a plurality of read reference blocks;
(c) a plurality of write reference blocks;
and
(d) a circuit utilizing said read and write reference blocks to program and read a select group of said memory cells wherein one of N gate voltages representing a predetermined binary value is applied to the memory cell of said select group of cells until a predetermined current is reached,
wherein each of said memory, read reference and write reference blocks having at least one row and one column of single transistor cells, each of said column of cells arranged in NAND type architecture having two select transistors and each of said cells having a floating gate for storing more than a single data bit of information within each cell.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 08/515,188Filed 15 Aug 1995
Granted: 21 Jan 1997
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 11/5621
Using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency: using charge storage in…
G11C 11/5628
Using charge storage in a floating gate: programming or writing circuits; Data input circuits
G11C 11/5642
Using charge storage in a floating gate: sensing or reading circuits; Data output circuits