Address transition detection sensing interface for flash memory having multi-bit cells

A method for determining a state of a memory cell, the method comprising the steps of:

• comparing a cell charge level of a first memory cell to a first reference and outputting a first result;
• selecting between second and third references in response to the first result;
• providing the first reference in place of the selected one of the second and third references for a predetermined period of time following output of the first result;
• and
• comparing the cell charge level of the first memory cell to the selected one of the second and third references and outputting a second result.

Sensing circuitry for determining a state of a memory cell, the sensing circuitry comprising:

• a first sense amp to compare a cell charge level of a first memory cell to a first reference and output a first result;
• reference selection circuitry coupled to the first sense amp, the reference selection circuitry to select between second and third references in response to the first result;
• a second sense amp, coupled to the reference selection circuitry, the second sense amp to compare the cell charge level of the first memory cell to the selected one of the second and third references and output a second result;
• and
• first forcing circuitry coupled to the second sense amp and to the reference selection circuitry, the first forcing circuitry to provide the first reference in place of the selected one of the second and third references to the second sense amp for a predetermined period of time following output of the first result.

A computer system, comprising:

• a processor;
• and
• a memory device coupled to the processor, the memory device having a memory cell array and sensing circuitry for determining a state of a memory cell of the array upon request from the processor, the sensing circuitry including:
• a first sense amp for comparing a cell charge level of a first memory cell to a first reference and outputting a first result;
• reference selection circuitry for selecting between second and third references in response to the first result;
• a second sense amp for comparing the cell charge level of the first memory cell to the selected one of the second and third references and outputting a second result;
• and
• first forcing circuitry for providing the first reference in place of the selected one of the second and third references to the second sense amp for a predetermined period of time following output of the first result.