Low current reduced area programming voltage detector for flash memory

A voltage detector circuit for determining when a first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value, comprising:

• a plurality of resistive devices coupled in series between the first supply voltage and system ground;
• a first transistor coupled to the first supply voltage and an output node, the first transistor receiving a first biasing voltage that varies as the first supply voltage ramps towards its final value from a first node defined between a first pair of resistive devices, the first transistor being operative to set the output node to a logic high level when the first supply voltage exceeds the predetermined voltage;
• a second transistor coupled to system ground and the output node, the second transistor receiving a second biasing voltage that varies as the first supply voltage ramps towards its final value from a second node defined between a second pair of resistive devices, wherein a difference between the second biasing voltage and system ground is equal to a difference between the first biasing voltage and the first supply voltage, the second transistor being operative to set the output node to a logic low level when the first supply voltage is less than the predetermined voltage;
• and
• a third transistor coupled between the second transistor and system ground, the third transistor receiving a third biasing voltage from a third node defined between a third pair of resistive devices.

A nonvolatile memory device comprising:

• an array of memory cells;
• a first input for receiving a first supply voltage for programming the array of memory cells, wherein the first supply voltage is selectively coupled to the array of memory cells;
• a second input for receiving a second supply voltage for operating circuitry of the nonvolatile memory device, wherein the second supply voltage is selectively coupled to the array of memory cells;
• a voltage detector circuit coupled to the first and second inputs for determining when the first supply voltage exceeds a predetermined voltage as the first supply voltage ramps towards its final value, the voltage detector circuit comprising:
• a plurality of resistive devices coupled in series between the first supply voltage and system ground;
• a first transistor coupled to the first supply voltage and an output node, the first transistor receiving a first biasing voltage that varies as the first supply voltage ramps towards its final value from a first node defined between a first pair of resistive devices, the first transistor being operative to set the output node to a logic high level when the first supply voltage exceeds the predetermined voltage;
• a second transistor coupled to system ground and the output node, the second transistor receiving a second biasing voltage that varies as the first supply voltage ramps towards its final value from a second node defined between a second pair of resistive devices, wherein a difference between the second biasing voltage and system ground is equal to a difference between the first biasing voltage and the first supply voltage, the second transistor being operative to set the output node to a logic low level when the first supply voltage is less than the predetermined voltage;
• and
• a third transistor coupled between the second transistor and system ground, the third transistor receiving a third biasing voltage from a third node defined between a third pair of resistive devices.

A voltage detector circuit for detecting whether a supply voltage exceeds a predetermined voltage comprising:

• a plurality of resistive devices coupled to define a first node, a second node, and a third node between the supply voltage and system ground;
• a first transistor having a gate coupled to the first node, a source coupled to the supply voltage, and a drain coupled to a first output node;
• a second transistor having a gate coupled to the second node, a source coupled to the first output node, and a drain;
• a third transistor having a gate coupled to the third node, a source coupled to system ground, and a drain coupled the drain of the second transistor;
• a fourth transistor having a gate coupled to the first output node, a source coupled to a second supply voltage, and a drain coupled to a second output node;
• a fifth transistor having a gate coupled to the first output node, a source, and a drain coupled to the second output node;
• a sixth transistor having a gate coupled to the third node, a drain coupled to the source of the fifth transistor, and a source;
• a seventh transistor having a gate coupled to the supply voltage, a source coupled to system ground, and a drain coupled to the source of the sixth transistor;
• and
• an eighth transistor having a gate coupled to the supply voltage, a source coupled to the second supply voltage, and a drain coupled to the second output node.