Method and device for selectively locking write access to blocks in a memory array using write protect inputs and block enabled status

A circuit for selectively locking write access to a block of a flash cell array in a flash memory device, comprising:

• circuit for receiving a lock command over a host bus, the lock command specifying the block of the flash cell array from among at least one available block in the flash cell array;
• circuit for disabling a block data row decoder for a block data area of the block, and enabling a block status row decoder for a block status area of the block;
• circuit for programming a lock cell in the block status area to a first logic state, such that the first logic state of the lock cell indicates that the block has a write access lock;
• circuit for receiving a write command targeted for the block, the write command specifying a program or erase operation on the block;
• circuit for sensing a write protect input from a write protect pin of the flash memory device, the write protect input indicating whether the write access lock is enabled or disabled;
• circuit for reading a lock bit from the lock cell and storing the lock bit into a block enabled status bit in a block status register corresponding to the block if the write protect input indicates that the write access lock is enabled, and if the block enabled status bit in the block status register corresponding to the block indicates that the block has the write access lock;
• circuit for signaling an error if the write protect input indicates that the write access lock is enabled, and if the block enabled status bit in the block status register corresponding to the block indicates that the block has the write access lock.

A flash memory device, comprising:

• a flash cell array comprising a block, the block comprising a block data area and a block status area, the block status area comprising a lock cell indicating whether the block has a write access lock;
• a block status register circuit comprising a block status register, the block status register storing a block enabled status bit for the block;
• a circuit for sensing a write protect input from a write protect pin of the flash memory device the write protect input indicating whether the write access lock is enabled or disabled:
• a flash array controller circuit receiving a program or erase command over a host bus targeted for the block, the flash array controller circuit reading a lock bit from the lock cell and storing the lock bit into the block enabled status bit in the block status register for the block after receiving the program or erase command, the flash array controller signaling an error if the write protect input indicates that the write access lock is enabled and if the block enabled status bit in the block status register for the block indicates that the block has the write access lock.

A computer system, comprising:

• main memory means storing a set of write data for a program operation;
• central processing means reading the write data from the main memory means and transferring a write command and the write data over a host bus;
• circuit for inhibiting the program operation to a block of a non-volatile memory cell array by maintaining a lock cell, the circuit for inhibiting comprising:
• circuit for sensing a write protect input from a write protect pin coupled to the host bus, the write protect input indicating whether the write access lock is enabled or disabled;
• circuit for reading a lock bit from the lock cell and storing the lock bit into a block enabled status bit in a block status register corresponding to the block if the write protect input indicates that the write access lock is enabled, and if the block enabled status bit in the block status register corresponding to the block indicates that the block has the write access lock.

A computer system, comprising:

• main memory means storing a set of write data for a program operation;
• central processing means reading the write data from the main memory means and transferring a write command and the write data over a host bus;
• a flash memory device inhibiting the program operation to a block of a flash cell array by maintaining a lock bit in a block status area of the block, the flash memory device comprising:
• a block status register circuit having a block status register, the block status register storing a block enabled status bit for the block;
• a circuit for sensing a write protect input;
• a flash array controller circuit receiving the write command over the host bus targeted for the block, the flash array controller circuit reading the lock bit and storing the lock bit into the block enabled status bit in the block status register for the block after receiving the write command or an erase command, the flash array controller circuit performing the program operation on the block if the write protect input indicates that a write access lock is disabled or if the lock bit indicates that the block does not have a write access lock the flash array controller circuit signaling an error if the write protect input indicates that the write access lock is enabled and the block enabled status bit in the block status register for the block indicates that the block bas the write access lock.

A method for detecting whether a block in a memory array is write protected, the method comprising the steps of:

• testing a flag to determine if the flag indicates that the block is write protected, the flag indicating that the block is write protected if a block enabled bit in a block Status register indicates the block is write protected and a write protect input is enabled;
• if the flag indicates that the block is write protected, then
• reading a block status from the memory array;
• updating the block enabled bit in the block status register from the block status;
• testing the flag to determine if the block is write protected;
• and
• signaling an error if the block is write protected.