Pipeline information processing circuit for floating point operations

An operation unit for floating point arithmetic operations, comprising:

• first operation means which has a bit width sufficient for carrying out a first operation, and can be operated in a first operation mode for carrying out the first operation and a second operation mode for carrying out a second operation,
• second operation means having a bit width sufficient at least for carrying out the second operation,
• third operation means which has a bit width sufficient for carrying out the first operation, and can be operated in the first operation mode and the second operation mode,
• fourth operation means having a bit width sufficient at least for carrying out the second operation, and
• fifth operation means which has a bit width sufficient for carrying out the first operation, and is operated in the first operation mode, the second operation mode and a third operation mode for carrying out two different sets of second operations are carried out at a same time.

A pipeline information processing circuit comprising:

• a register file composed of a plurality of registers designated by register numbers for storing a plurality of data;
• an arithmetic logic unit capable of performing a first arithmetic operation of multiple-precision by receiving two multiple-precision data items respectively through first and second input ports to perform said first arithmetic operation and outputting a result of said first arithmetic operation through an output port;
• each of said first and second input ports comprising a plurality of fields each capable of independently receiving a single-precision data item, said output port comprising a plurality of fields each capable of independently outputting a single-precision data item in correspondence with one of said fields of each of said first and second input ports;
• said arithmetic logic unit being capable of performing a plurality of single-precision second arithmetic operations in parallel by carrying out respective separate arithmetic operations of said single-precision data items input through the corresponding fields of said first input port and said single-precision data items input through the corresponding fields of said second input port as executed data, said arithmetic unit providing said executed data on said plurality of fields of said output port;
• an output register connected to said output port of said arithmetic logic unit and to said register file, said output register comprising a plurality of fields and configured to store said respective executed data from each of said plurality of fields of said outport into a corresponding one of said plurality of fields of said output register, said output register transferring said executed data to said register file as writeback data;
• and
• a controller connected with said register file and said arithmetic logic unit and said output register and provided witch a plurality of selectors through which one of said executed data and said writeback data is transferred in a by-pass configuration from at least one of (1) said fields of said output port of said arithmetic logic unit and (2) at least one of said fields of said output register to any of the fields of said first and second input ports of said arithmetic logic unit, and through which data is transferred in a non-bypass configuration from said register file to any of said fields of said first and second input ports of said arithmetic logic unit.

A pipeline information processing circuit for floating point arithmetic operation comprising:

• a register file composed of a plurality of registers designated by register numbers for storing a plurality of data;
• an arithmetic logic unit capable of performing a first arithmetic operation of a multiple-precision by receiving two data items of said multiple-precision respectively through first and second input ports to perform said first arithmetic operation and outputting a result of said first arithmetic operation through an output port as executed data, said arithmetic logic unit writing said executed data back to said register file as writeback data,
• each of said first and second input ports comprising a plurality of fields each capable of independently receiving a data item of a single-precision, said output port comprising a plurality of fields each capable of independently outputting a data item of said single-precision in correspondence with one of said fields of each of said first and second input ports;
• said arithmetic logic unit being capable of performing a plurality of second arithmetic operations of said single-precision in parallel by carrying out respective separate arithmetic operations of said data items input through said respective fields of said first input port and said data items input through the corresponding fields of said second input port;
• and
• a bypass controller connected with said register file and said arithmetic logic unit and provided with a plurality of selectors through which the data is transferred selectively from said register file and/or at least one of said fields of said output port of said arithmetic logic unit to any one of the fields of said first and second input ports of said arithmetic logic unit, said bypass controller being provided further with storage means for storing flags indicating whether the data transferred from said output port of said arithmetic logic unit is valid or not,
• wherein said pipeline information processing circuit has at least a fetch cycle, a decode cycle, an execute cycle, and a writeback cycle, and when a first instruction is in said decode cycle, a second instruction is in said execute cycle, and a third instruction is in said writeback cycle, a register number corresponding to where a result of said third instruction is to be transferred to in said register file is compared to a register number corresponding to where a result of said second instruction is to be transferred to in said register file and is also compared to a register number corresponding to an operand of said first instruction which is to be taken but has not yet been taken for a calculation in said arithmetic logic unit, and if the register number corresponding to said third instruction is coincident with the register number corresponding to said first instruction, said writeback data is used as said operand, and if the register number corresponding to said third instruction is not coincident with the register number corresponding to said first instruction but is coincident with the register number corresponding to said second instruction, said executed data is used as said operand, otherwise data from said register file is used as said operand.