Real time programmable signal processor architecture

A programmable real time signal processor apparatus designed for semiconductor integration, which receives regularly clocked data signals from means external said signal processor apparatus, and processes said regularly clocked data signals thereby generating processed data signals which are available external to said processor apparatus as regularly clocked output signals, comprising:

• a) at least one data signal receiving means for receiving said regularly clocked data signals from said means external said signal processor apparatus, each data signal receiving means including means for writing data to a plurality of desired first address locations in a multiported central memory unit in a repeated sequential fashion;
• b) said multiported central memory unit coupled to said at least one data signal receiving means, said multiported central memory unit for storing said received data signals;
• c) a digital processor means coupled to said multiported central memory unit, for obtaining said data signals from said first addresses of said multiported central memory unit, for processing said data signals and thereby generating processed data signals, and for sending said processed data signals for storage in second address locations of said multiported central memory unit;
• d) at least one data output means coupled to said multiported central memory unit, for obtaining in a repeated sequential fashion said processed data signals from said second address locations of said multiported central memory unit at a rate related to the rate of said regularly clocked data signals, and for providing said processed data signals as regularly clocked output signals available external to said processor apparatus,
• wherein substantially all signal data received by said processor apparatus flows directly from said at least one said data signal receiving means to said multiported central memory unit and said digital processor means obtains data signals for processing substantially only from said multiported central memory unit and provides said processed data signals substantially only to said multiported central memory unit, and wherein said data signal receiving means and said output means handle data flow into and out of said processor apparatus and permit said digital processor means to function substantially free of data input interrupts.

A system for implementing in substantially integrated circuit format different circuits defined by textual or graphical high level description, comprising:

• a) a development system having
• 1) memory means storing a cell library, said cell library including a plurality of functional block elements useful in implementing said different circuits, each functional block defined by a set of instructions,
• 2) circuit definition entry means for choosing said functional block elements of said cell library and for defining interconnections between said functional block elements, said circuit definition entry means including means for entering parameters for a plurality of functional block elements chosen as part of a desired circuit,
• 3) processor means for compiling said set of instructions and said parameters according to a desired algorithm to create microcode for at least one signal processor apparatus whereby said at least one signal processor apparatus can thereby implement said desired circuit;
• b) said signal processor apparatus, for receiving regularly clocked data signals generated external to said signal processor apparatus, for processing said data signals according to said microcode thereby generating processed data signals, and for making said processed data signals available as regularly clocked output signals having a data rate related to the data rate of said regularly clocked data signals to means external to said processor apparatus, said signal processor apparatus including
• 1) port means for receiving said regularly clocked data signals and for receiving said microcode from said development system,
• 2) a program memory including a program bus, said program memory coupled to said port means for receiving and storing said microcode,
• 3) a multiported central memory unit including a data bus, said multiported central memory unit coupled to said port means, said port means including means for forwarding said received data signals to desired locations in said multiported central memory unit, and said multiported central memory unit for storing said received data signals;
• 4) a digital processor means coupled to said multiported central memory unit and to said program memory, for obtaining said data signals from said multiported central memory unit, for processing said data signals according to said microcode stored in said program memory, and thereby generating processed data signals, and for sending said processed data signals for storage in said multiported central memory unit, and
• 5) an output means coupled to said multiported central memory unit, for obtaining said processed data signals from said multiported central memory unit, and for making said processed data signals available to said means external said processor apparatus as regularly clocked output signals having a data rate related to the data rate of said regularly clocked data signals.

A method for processing information in a real time signal processor apparatus designed for semiconductor integration, said processor apparatus having a data signal receiving means for receiving regularly clocked data signals from a means external to said processor apparatus, a multiported central memory unit coupled to said data signal receiving means, a digital processor means coupled to said multiported central memory unit, and at least one output port coupled to said multiported central memory unit, said method comprising for an operating mode of said processor apparatus:

• a) receiving said regularly clocked data signals at said data signal receiving means;
• b) forwarding said received data signals in a repeated sequential fashion to a plurality of desired first locations in said multiported central memory unit;
• c) causing said digital processor means to obtain said data signals from said multiported central memory unit;
• d) processing said data signals in said digital signal processor to generate processed data signals;
• e) sending said processed data signals from said digital processor means to said multiported central memory unit for storage in desired second locations in said multiported central memory unit;
• f) causing said output port to obtain said processed data signals from said desired second locations in a repeated sequential fashion and to make said processed data signals available to means external to said processor apparatus as regularly clocked output signals having a data rate related to said regularly clocked data signals,
• wherein substantially all signal data received by said processor apparatus flow directly from said at least one said data signal receiving means to said multiported central memory unit and said digital processor means obtains data signals for processing substantially only from said multiported central memory unit and provides said processed data signals substantially only to said multiported central memory unit.