Advanced parallel array processor(APAP)

A computer system, comprising:

• a control unit, an interconnection system and a processing array for parallel processing having nodes which are interconnected with the distribution system to other processing nodes, wherein:
• the control unit is programmable and has means for enabling the processing array having an array of processing elements to operate in coordination and which also enables a system control program to operate subsets of the parallel array with each subset dedicated to different applications or different phases of a single application program's processing, wherein
• the interconnection system provides physical connections between the control unit and the elements of the parallel array of processing elements enabling data and control transfers which are completely independent of the transfer of data between elements of the processing array,
• the interconnection system distributes functions associated with data transfer between elements of the processing array and distributed functions embedded in processing node software, and
• the processing array provides non-shared memory and compute services and which are partitioned and the processing array is scalable
• further comprising means for data transfer control including
• a set of two or more ports at each processing element for transfer of data from a processing element toward a destination,
• registers and counters in each processing element for each port of each processing element to manage the sending and receiving of a single block of data through the port where a block of data is variable length as determined by the application or system operating software,
• hardware paths within each port of each processing element that transition on the basis of transfer counts so as to permit software controls to setup in advance actions to take in the event of buffer full, end of message, and other events,
• means for set up of each processing element's port count, address and control features to initiate transfers out, or prepare for a transfer in,
• control means within the processing element having software dedicated to end of message indication on a particular port to completely service routing and synchronization requirements resulting from the message,
• a combination hardware and software means for data transfer between processing elements to be managed as circuit switched traffic, store and forward packet switched traffic, or communication load driven combinations of the two approaches, thereby permitting applications which could generate possible deadlocks due to data transfer blocking to include protective features while applications without such risks will not incur a performance penalty,
• software means for operating at an end of message indication for an input end of the message to provide services the application requires, and further including:
• means for holding data and setting status suitable for application program polling,
• means for initiating application programs that have entered wait states, thereby providing I/O synchronization, initiate output message traffic to provide confirmation to sender,
• means for controlling inter-processing element data traffic software which permits applications to embed within I/O control software and further including:
• means for providing a combination of data transfer and data reduction operations that are required to perform operations across parallel processor, including operations where a Vector Inner Product requires a sum reduction involving tree like data transfers in combination with adds, such that an I/O program can perform the complete function, thereby providing the application with the appearance of dedicated hardware,
• means for performing data structure transformations that reshape complex entities, including data arrays when they are moved to the parallel processing array,
• means for imposing logical topologies over physical topologies, including in a machine wired like a hypercube, I/O routing programs can provide a logical NEWS topology for a particular application, and
• means for performing data access conversions including those required for FFT butterfly processing, bit reversed data addressing, and perfect shuffle data transformations.