US 5,589,765 AGranted

Method for final testing of semiconductor devices

AssigneeTexas Instruments Incorporated

InventorsDale V. Ohmart, Willie B. Benitez, III, Deogracias D. Marrero, Douglas J. Mirizzi

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Abstract

A method is provided for more efficiently and inexpensively testing semiconductor devices by an automated process of monitoring the performance of the test equipment and certifying that it is working properly, both before and after the actual tests of the devices are conducted. If the automated process can certify that the test equipment was working properly, prior and subsequent to the actual tests of the devices, then it can be assumed that the actual tests were performed correctly and the results are valid. Those devices that "passed" the actual tests are then ready for the next step in the fabrication process, or typically ready to be shipped to the customer. If the test equipment's performance degrades significantly during the actual tests, then the results of the actual tests are considered invalid. Consequently, the test equipment can be repaired or recalibrated and all of the devices retested.

Claims18

Dependent claims

A method for final testing a lot consisting of a predetermined plurality of semiconductor devices, comprising the steps of:

testing operation of a test system relative to a predetermined set of test system performance characteristics;
if said test system fails to operate in accordance with said predetermined set of test system performance characteristics, repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics;
certifying that said test system is operating in accordance with said predetermined set of test system performance criteria;
testing a plurality of semiconductor device performance characteristics of each of said lot of semiconductor devices with said test system, said testing resulting in passing semiconductor devices operating in accordance with said plurality of semiconductor device performance characteristics and failing semiconductor devices not operating in accordance with said plurality of semiconductor device performance characteristics;
subsequent to said testing of said lot of semiconductor devices, testing operation of said test system relative to said predetermined set of test system performance characteristics;
if said test system fails to operate in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices
repairing said test system and retesting operation of said test system until said test system operates in accordance with said predetermined set of test system performance characteristics,
following repair of said test system restarting testing each of said lot of semiconductor devices and subsequent to said restart of testing of said lot of semiconductor devices retesting operation of said test system;
if said test system operates in accordance with said predetermined set of test system performance criteria subsequent to said testing of said lot of semiconductor devices, recertifying that said test system is operating in accordance with said predetermined set of test system performance criteria;
and
packing and shipping said passing semiconductor devices.

8 more elements

A method for final testing of a lot of a predetermined number of semiconductor integrated circuits, comprising the steps of:

loading said lot of said semiconductor integrated circuits into a semiconductor device test handler;
measuring a plurality of tester performance characteristics of a semiconductor device tester coupled to said test handler;
measuring a plurality of test handler performance characteristics of said test handler;
comparing said plurality of tester performance characteristics to a predetermined set of tester criteria and said plurality of test handler performance characteristics to a predetermined set of test handler criteria;
if either said tester fails to operate in accordance with said predetermined set of tester criteria or said test handler fails to perform in accordance with said teat handler criteria, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria;
if both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of teat handler criteria, measuring a plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester;
sorting each of said lot of said semiconductor integrated circuits at an output of said test handler into passing and failing groups in accordance with said measured plurality of semiconductor integrated circuit performance characteristics;
remeasuring said plurality of tester performance characteristics subsequent to said measuring said plurality of semiconductor performance characteristics of said lot of semiconductor integrated circuits;
remeasuring said plurality of test handler performance characteristics subsequent to said measuring said plurality of semiconductor performance characteristics of said lot of semiconductor integrated circuits;
recomparing said remeasured plurality of tester performance characteristics to said predetermined set of tester criteria and said remeasured plurality of test handler performance characteristics to said predetermined set of test handler criteria;
if either said tester fails to operate in accordance with said predetermined set of tester criteria on remeasurement or said test handler fails to perform in accordance with said teat handler criteria on remeasurement, repairing said tester and said test handler and remeasuring said tester performance characteristic and said test handler performance characteristic until both said tester operates in accordance with said predetermined set of tester criteria and said test handler operates in accordance with said predetermined set of test handler criteria, and thereafter remeasuring said plurality of semiconductor integrated circuit performance characteristics of each of said lot of said semiconductor integrated circuits with said tester;
if both said tester operates in accordance with said predetermined set of tester criteria on remeasurement and said test handler operates in accordance with said predetermined set of teat handler criteria on remeasurement, then packing and shipping said semiconductor integrated circuits in said passing group.

9 more elements

Dependencies are inferred from the claim text.