CMOS EEPROM cell with tunneling window in the read path
AssigneeAdvanced Micro Devices, Inc.
InventorsJonathan Lin, Jack Z. Peng, Radu Barsan, Sunil Mehta
Life of this patent
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Abstract
A CMOS memory cell including PMOS and NMOS transistors with a common floating gate. The CMOS memory cell includes a first capacitor connecting a first control voltage to the common floating gate and a second tunneling capacitor connected from the common floating gate to the source of the NMOS transistor. The tunneling capacitor includes a tunneling oxide region utilized to charge or discharge the floating gate during program or erase. The CMOS cell further includes a pass transistor with a source to drain path connecting the source of the NMOS transistor to a second control voltage.
Claims6
A memory cell comprising:
- a PMOS transistor having a drain forming an output node, a source and a channel between the source and drain underlying a common floating gate;
- an NMOS transistor having a drain coupled to the output node, a source and a channel between the source and drain of the NMOS transistor underlying the common floating gate;
- a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate;
- a tunneling capacitor having a first terminal coupled to the common floating gate and a second terminal coupled to the source of the NMOS transistor.
A programmable logic device (PLD) comprising:
- a sense amplifier having a product term (PT) input and a product term ground (PTG) input;
- a plurality of memory cells, each comprising:
- a PMOS transistor having a drain coupled to the PT line, a source and a channel between the source and drain underlying a common floating gate;
- an NMOS transistor having a drain coupled to the PT line, a source and a channel between the source and drain of the NMOS transistor underlying the common floating gate;
- a capacitor having a first terminal forming a control gate and a second terminal coupled to the common floating gate;
- a tunneling capacitor having a first terminal coupled to the common floating gate and a second terminal coupled to the source of the NMOS transistor;
- and
- a pass transistor having a drain connected to the source of the NMOS transistor, a source connected to the PTG line, and a gate forming an enable input.
Dependencies are inferred from the claim text.