Method and apparatus for the reduction of tablewalk latencies in a translation look aside buffer

In a computer system comprising a processor and memory, wherein accesses to memory are performed by issuing a virtual address to memory, an apparatus for performing a translation from a virtual address to a physical address comprising:

• a memory management unit (MMU) comprising a data path for receiving a context of a memory access and a virtual address and outputting a physical address to access memory and a controller for controlling translation of virtual addresses to physical addresses;
• a translation look aside buffer comprising;
• a page table memory comprising a plurality of levels of a page table, an initial level of the page table being identified as a root level, said page table memory storing page table pointers (PTPs) which provide a base address of a table in a next higher level of a page table and page table entries (PTEs) which provide information to translate the virtual address to the physical address;
• and
• a tag memory comprising tags identifying PTEs and PTPs, said tags identifying a table comprising virtual PTP tags for PTPs located in at least one predetermined higher level that is higher than the root level, said tags providing a pointer to a corresponding entry in the page table;
• said MMU controller generating a compare virtual PTP tag if a TLB miss occurs when to access a tag identifying a PTE corresponding to the virtual address, said compare virtual PTP tag generated from the context of the memory address and a predetermined portion of the virtual address and the content of the memory address where the miss occurred, said compare virtual PTP tag compared to stored virtual PTP tags stored in the tag memory such that if the compared virtual PTP tag and one of the stored virtual PTP tags match, said controller providing a pointer to the corresponding PTP at the predetermined higher level of the page table without performing a page table walk initiating at the root level through the lower level page tables;
• wherein the time expended for performing a page table walk is minimized.

In a computer system comprising a processor and memory, wherein accesses to memory are performed by issuing a virtual address to memory, said system further comprising a translation look aside buffer comprising a tag memory and a page table memory, said page table memory comprising a plurality of levels of a page table, an initial level of the page table being identified as a root level, said page table memory storing page table pointers (PTPs) which provide a base address of a table in a next higher level of a page table and page table entries (PTEs) which provide information to translate the virtual address to the physical address, said tag memory comprising tags identifying PTEs and PTPs, a method for performing a translation from a virtual address to a physical address comprising the steps of:

• storing virtual PTP tags for PTPs located in at least one predetermined higher level higher than the root level, said tags providing a pointer to a corresponding entry in the page table;
• and
• if a TLB miss occurs when trying to access a tag identifying a PTE corresponding to the virtual address;
• generating a compare virtual PTP tag, said compare virtual PTP tag generated from the context of the memory address and a predetermined portion of the virtual address and the content of the memory address where the miss occurred,
• comparing said compare virtual PTP tag to the stored virtual PTP tags stored in the tag memory, and
• if the compared virtual PTP tag and one of the stored virtual PTP tags match, providing a pointer to the corresponding PTP at the predetermined higher level of the page table without performing a page table walk initiated at the root level through the lower level page tables;
• wherein the time expended for performing a page table walk is minimized.