Field effect transistor having saturated drain current characteristic

In a field effect transistor comprising:

• a semiconductor region of a first conductivity type, a source and a drain provided at opposite ends of said semiconductor region, and
• gate means of p-type semiconductor material, provided adjacent to said semiconductor region, for defining a channel in said semiconductor region and for controlling the flow of drain current between said source and said drain,
• said drain and said gate means being adapted to be applied with a drain voltage and a gate bias voltage from external voltage sources, respectively, the improvement comprising:
• said semiconductor region being formed of a semiconductor material having a low impurity concentration;
• the product of the series resistance and the true transconductance of said field effect transistor being maintained less than one for low magnitudes of drain current irrespective of the gate bias voltage, thereby providing an unsaturated drain current versus drain voltage characteristic in the main operative state of said transistor;
• and
• said series resistance being the sum of the resistance in said source, the resistance from said source to said channel and the resistance of said channel.

In a field effect transistor comprising:

• a semiconductor region of a first conductivity type,
• a source and a drain provided at opposite ends of said semiconductor region, and
• gate means, provided adjacent to said semiconductor region, for defining a channel portion of said semiconductor region and for controlling the drain current between said source and said drain flowing through said channel portion, said channel portion having a length along the direction of flow of said drain current and a width transverse to the direction of flow of said current,
• said drain and said gate means being adapted to be applied with a drain voltage and a gate bias voltage from external voltage sources, respectively,
• the improvement wherein:
• said semiconductor region is formed of a semiconductor material having a low impurity concentration;
• and
• the product of the series resistance and the true transconductance of said field effect transistor is maintained less than one in at least a portion of the operative state of said transistor in which state a drain current is flowing, to provide substantially throughout said state an unsaturated drain current versus drain voltage characteristic for any operative value of said gate bias voltage,
• said series resistance being the sum of the resistance in the source, the resistance from said source to said channel portion and the resistance of said channel portion, and
• said semiconductor region includes first and second intrinsic semiconductor regions disposed at said opposite ends, and n-type semiconductor layers provided at said first and second intrinsic semiconductor regions, said gate means comprising a mesh of p-type semiconductor material provided along a boundary region between one of said intrinsic semiconductor regions and one of said n-type layers.

In a field effect transistor comprising:

• a semiconductor region of a first conductivity type,
• a source and a drain provided at opposite ends of said semiconductor region, and gate means, provided adjacent to said semiconductor region, for defining a channel portion of said semiconductor region, and for controlling drain current flow between said source and said drain through said channel portion, said channel portion having a predetermined length along the direction of said drain current flow and a predetermined width along the direction transverse to said drain current flow,
• said drain and said gate means being adapted to be applied with a drain voltage and a gate bias voltage from external voltage sources, respectively, the improvement wherein:
• said semiconductor region is formed of a semiconductor material having a low impurity concentration, and
• the product of the series resistance and the true transconductance of said field effect transistor is maintained less than one in at least a portion of the operative state of said transistor in which state there exists an unsaturated drain current versus drain voltage characteristic for any operative value of said gate bias voltage,
• said series resistance being the sum of the resistance in said source, the resistance from said source to said channel portion and the resistance of said channel portion, and
• said semiconductor region includes an intrinsic semiconductor region and n-type semiconductor layers provided on the ends of said intrinsic semiconductor region of which said source and said drain are provided, and in which said gate means comprises a mesh of p-type semiconductor material provided along a boundary region between the intrinsic semiconductor region and one of the n-type layers.

A field effect transistor comprising:

• a semiconductor region comprising a low doped n.sup.- layer and a high doped n.sup.+ layer of low resistance contiguous to said n.sup.- layer,
• a source provided at one end of said semiconductor region and having the same conductivity type as that of said n.sup.+ layer,
• a drain provided at the other end opposed to the one end of said semiconductor region and having the same conductivity type as that of said n.sup.- layer, said drain being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain and said source,
• a gate formed adjacent said semiconductor region to define a portion of said semiconductor region having predetermined dimensions, said gate being adapted to be applied with a gate voltage from an external voltage source,
• depletion layers extending from said gate, respectively, inwardly into said portion of said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• the degree of extension of said depletion layers into said portion of said semiconductor region being controlled by changes in said gate voltage, said channel having predetermined length and width in the absence of any applied voltage, said degree of extension of the depletion layers controlling said drain current, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel,
• wherein the length and width of said channel is selected so that the product of said transconductance and the sum of the resistance of said source, and said first series resistance and said second series resistance is maintained less than one in operative state of the transistor in which state a drain current is flowing.

A field effect transistor comprising:

• a semiconductor region comprising an intrinsic semiconductor region, a highly doped n.sup.+ layer of low resistance adjacent to one surface of said intrinsic semiconductor region and a low doped n.sup.- layer of high resistance coupled on the other surface of the intrinsic semiconductor region,
• a source provided on one end of said semiconductor region and having the same conductivity type as that of said n.sup.+ layer,
• a drain provided at the other end opposed to said one end of said semiconductor region and having the same conductivity type as that of said n.sup.- layer, said drain being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain and said source,
• gates formed adjacent to said semiconductor region to define a portion of said semiconductor region having predetermined dimensions, said gates being adapted to be applied with a gate voltage from an external voltage source,
• said gates being operative so that depletion layers extend from said gates, respectively, inwardly into said portion of said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• wherein the degree of extension of said depletion layers into said portion of said semiconductor region is controlled by changes in said gate voltage, said channel having predetermined length and width in the absence of any applied gate voltage, and wherein the degree of extension of the depletion layers controlling said drain current, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• the length and width of said channel being selected so that the product of said transconductance and the sum of the resistance of said source, said first series resistance and said second series resistance is maintained less than one in operative state of the transistor in which state a drain current is flowing.

A field effect transistor comprising:

• a semiconductor region comprising an intrinsic semiconductor region and n-type layers coupled respectively one and the other of two opposed surfaces of the intrinsic semiconductor region,
• a source and a drain both having the same conductivity type as that of said n-type layer and provided at the opposite ends of said semiconductor region, said drain being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain and said source,
• a gate comprising a mesh of p-type semiconductor material provided along a boundary region between the intrinsic region and one of the n-type layers, said gate being adapted to be applied with a gate voltage from an external voltage source,
• said gate being operative so that depletion layers extend from said gate, respectively, inwardly into said portion of said semiconductor region so as to face each other, thereby to define at least one current channel in said portion of said semiconductor region,
• wherein the degree of extension of said depletion layers into said portion of said semiconductor region is controlled by changes in said gate voltage, said channel having a predetermined length and width in the absence of any applied gate voltage, and wherein the degree of extension of the depletion layers controls said drain current, hereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• the length and width of said channel region is selected so that the product of said transconductance and the sum of the resistance of said source, said first series resistance and said second series resistance is maintained less than one in operative state of the transistor in which state a drain current is flowing.

A field effect transistor comprising:

• a semiconductor comprising an intrinsic semiconductor region and n-type layers coupled respectively to one and the other of two opposed surfaces of the intrinsic semiconductor region,
• a source and a drain both having the same conductivity type as that of said n-type layer and provided at the opposite ends of said semiconductor region, said drain being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain and said source,
• a gate comprising a mesh of p-type semiconductor material provided along a boundary region between the intrinsic semiconductor region and one of the n-type layers, said gate being adapted to be applied with a gate voltage from an external voltage source,
• said gate being operative so that depletion layers extend from said gate, respectively, inwardly into said portion of said semiconductor region so as to face each other, thereby to define at least one current channel in said portion of said semiconductor region,
• and wherein the degree of extension of said depletion layers into said portion of said semiconductor region is controlled by changes in said gate voltage, said channel having predetermined length and width in the absence of any applied gate voltage, and wherein the degree of extension of the depletion layers controls said drain current, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• wherein the length and width of said channel is selected so that the product of said transconductance and the sum of the resistance of said source, said first series resistance and said second series resistance is maintained less than one in operative state of the transistor in which state a drain current is flowing.

A field effect transistor comprising:

• a semiconductor region having a conductivity type and having an impurity concentration:
• source and drain semiconductor regions having the same conductivity type as that of said semiconductor region and provided at the opposite ends of said semiconductor region, said drain region being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain region and said source region,
• at least a pair of gates provided at opposite sides of said semiconductor region and having projections which are inserted in said semiconductor region so as to oppose to each other, said gates being adapted to be applied with a gate voltage from an external voltage source, said gates being operative in that depletion layers extend from the junction into said semiconductor region, respectively, inwardly into said semiconductor region so as to face each other and have a formation like the shape of said projections, thereby to define at least one current channel in said portion of said semiconductor region,
• wherein the degree of extension of said depletion layers into said semiconductor region is controlled by changes in said gate voltage, said channel having predetermined channel dimensions in the absence of any applied gate voltage, said degree of extension of the depletion layers controlling said drain current through said channel, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel,
• said impurity concentration of said semiconductor region and said predetermined dimensions being selected so that the product of said transconductance and the sum of said first and second series resistances is maintained less than one in an operative state of the transistor in which state a drain current flows.

A field effect transistor comprising:

• a first semiconductor layer having a first conductivity type,
• a channel layer provided over said first semiconductor layer and having said first conductivity type,
• a gate structure having a second conductivity type opposite to said first conductivity type, said gate structure being formed in said channel layer to define a plurality of channels,
• a second semiconductor layer provided on said channel layer and having said first conductivity type,
• a drain electrode provided on said first semiconductor layer,
• a source electrode provided on said second semiconductor layer, and
• a gate electrode attached to said gate structure, the improvement comprising:
• the configuration of doping concentration of said first, second and channel layers are such that the product of the series resistance and the true transconductance of said field effect transistor is maintained less than one in the operative state of said transistor in which state a drain current is flowing to provide an unsaturated drain current versus drain voltage characteristic.

A field effect transistor comprising:

• a semiconductor region having a first conductivity type and having an impurity concentration:
• source and drain semiconductor regions both having the same conductivity type as that of said semiconductor region and provided at the opposite ends of said semiconductor region, said drain region being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain region and said source region,
• a plurality of gates having a second conductivity type opposite to said first conductivity type and provided at opposite sides of said semiconductor region to define therein a portion of said semiconductor region wherein each gate comprises a ring having a thin thickness relative to the diameter thereof, said gates being adapted to be applied with a gate voltage from an external voltage source,
• said gates being operative so that depletion layers extend from the junction of said gates and said semiconductor region, respectively, inwardly into said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• and wherein the degree of extension of said depletion layers into said semiconductor region is controlled by the changes in said gate voltage, said channel has predetermined channel dimensions in the absence of any applied gate voltage, and said degree of extension of the depletion layers controls said drain current through said channel, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• said impurity concentration of said semiconductor region and said predetermined dimensions being selected so that the product of said transconductance and the sum of said first and second series resistances is maintained less than one in the operative state of the transistor in which state a drain current flows.

A field effect transistor comprising:

• a semiconductor region having a first conductivity type and comprising a low doped n.sup.- layer and a highly doped n.sup.+ layer of low resistance coupled on said n.sup.- layer,
• a source provided at one end of said semiconductor region and having the same conductivity type as that of said semiconductor region,
• a drain semiconductor region provided at the opposite end of said semiconductor region and having the same conductivity type as that of said semiconductor region, said drain region being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain region and said source region,
• a plurality of gate elements having a second conductivity type opposite to said first conductivity type and formed adjacent to said semiconductor region to define therebetween a portion of said semiconductor region having predetermined dimensions, said gate elements being adapted to be applied with a gate voltage from an external voltage source,
• said gate elements being operative in that depletion layers extend from the junction of said gate elements and said semiconductor region, respectively, inwardly into said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• and wherein the degree of extension of said depletion layers into said semiconductor region is controlled by changes in said gate voltage, said channel has predetermined channel dimensions in the absence of any applied gate voltage, and said degree of extension of the depletion layers controls said drain current through said channel, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• said predetermined dimensions being selected so that the product of said transconductance and the sum of said first and second series resistances is maintained less than one in the operative state of the transistor in which state a drain current flows.

A field effect transistor comprising:

• a semiconductor region having a first conductivity type and comprising an intrinsic semiconductor region, a highly doped n.sup.+ layer of the low resistance coupled to one surface of the intrinsic semiconductor region and a low doped n.sup.- layer of high resistance coupled on the other surface of the intrinsic semiconductor region,
• a source semiconductor region provided on one end of said semiconductor region and having the same conductivity type as that of said semiconductor region,
• a drain semiconductor region provided at the opposite end of said semiconductor region and having the same conductivity type as that of said semiconductor region,
• said drain region being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain region and said source region,
• a plurality of gate elements having a second conductivity type opposite to said first conductivity type and being formed adjacent to said semiconductor region to define therebetween a portion of said semiconductor region having predetermined dimensions, said gate elements being adapted to be applied with a gate voltage from an external voltage source,
• depletion layers extend from the junction of said gates and said semiconductor region, respectively, inwardly into said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region, and wherein
• the degree of extension of said depletion layers into said semiconductor region is controlled by changes in said gate voltage, said channel has predetermined channel dimensions in the absence of any applied gate voltage, and wherein the degree of extension of the depletion layers controls said drain current through said channel, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second resistance through said channel,
• said predetermined dimensions being selected so that the product of said transconductance and the sum of said first and second series resistances is maintained less than one in the operative state of the transistor in which state a drain current flows.

A field effect transistor comprising:

• a semiconductor region having a first conductivity type and having an impurity concentration and comprising an intrinsic semiconductor region and n-type layers coupled respectively one and the other of two opposed surfaces of the intrinsic semiconductor region,
• source and drain semiconductor regions having the same conductivity type as that of said semiconductor region and provided at the opposite ends of said semiconductor region, said drain region being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain region and said source region,
• a plurality of gate elements comprising a mesh of p-type semiconductor provided along a boundary region between the intrinsic semiconductor region and one of the n-type layers,
• said gate elements being adapted to be applied with a gate voltage from an external voltage source,
• said gate elements being operative in that depletion layers extend from the junction of said gate elements and said semiconductor region, respectively, inwardly into said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• and wherein the degree of extension of said depletion layers into said semiconductor region is controlled by changes in said gate voltage, said channel has predetermined channel dimensions in the absence of any applied gate voltage, and said degree of extension of the depletion layers controls said drain current through said channel, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• said impurity concentration of said semiconductor region and said predetermined dimensions being selected so that the product of said transconductance and the sum of said first and second series resistances is maintained less than one in the operative state of the transistor in which state a drain current flows.

A field effect transistor comprising:

• a semiconductor region having a first conductivity type and having an impurity concentration and comprising an intrinsic semiconductor region and n-type layers coupled respectively one and the other of two opposed surfaces of the intrinsic semiconductor region,
• source and drain semiconductor regions having the same conductivity type as that of said semiconductor region and provided at opposite ends of said semiconductor region, said drain region being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain region and said source region,
• a plurality of gate elements comprising a mesh of p-type semiconductor provided along a boundary region between the intrinsic semiconductor region and one of the n-type layers, said gate elements being adapted to be applied with a gate voltage from an external voltage source,
• said gate elements being operative in that depletion layers extend from the junction of said gate elements and said semiconductor region, respectively, inwardly into said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• and wherein the degree of extension of said depletion layers into said semiconductor region is controlled by changes in said gate voltage, said channel has predetermined channel dimensions in the absence of any applied gate voltage, and said degree of extension of the depletion layers controls said drain current through said channel, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• said impurity concentration of said semiconductor region and said predetermined dimensions being selected so that the product of said transconductance and the sum of said first and second series resistances is maintained less than one in the operative state of the transistor in which state a drain current flows.

In a field effect transistor comprising:

• a semiconductor region of a first conductivity type,
• a source and a drain provided at opposite ends of said semiconductor region, and
• gate means of p-type semiconductor material, provided adjacent to said semiconductor region, for defining a channel portion of said semiconductor region and for controlling the flow of drain current between said source and said drain through said channel portion, said channel portion having a predetermined length along the direction of said drain current and a predetermined width along the direction transverse to the flow of said drain current, said drain and said gate means being adapted to be applied with a drain voltage and a gate bias voltage from external voltage sources, respectively,
• the improvement wherein:
• said semiconductor region is formed of a semiconductor material having a low impurity concentration;
• the product of the series resistance and the true transconductance of said field effect transistor is maintained less than one in at least a portion of the operative state of said transistor in which state there exists an unsaturated drain current versus drain voltage characteristic for any operative value of said gate bias voltage;
• and
• said series resistance being the sum of the resistance in said source, the resistance from said source to said channel portion and the resistance of said channel portion.

A field effect transistor comprising:

• a semiconductor region having one conductivity type and having an impurity concentration,
• a source and a drain both having the same conductivity type as that of said semiconductor region and provided at the opposite ends of said semiconductor region, said drain being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain and said source,
• at least a pair of gates provided at opposite sides of said semiconductor region and having projections which are inserted in said semiconductor region so as to oppose to each other, said gates being adapted to be applied with a gate voltage from an external voltage source,
• depletion layers extending from said gates, respectively, inwardly into a portion of said semiconductor region so as to face each other and being formed according to the shape of said projections, thereby to define at least one current channel in said portion of said semiconductor region,
• the degree of extension of said depletion layers into said portion of said semiconductor region being controlled by changes in said gate voltage, said channel having a predetermined length and width in the absence of any applied gate voltage, said degree of extension of the depletion layers controlling said drain current, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel, and
• said impurity concentration of said semiconductor region and the length and width of said channel being selected so that the product of said transconductance and the sum of the resistance of said source, said first series resistance and said second series resistance is maintained less than one in the operative state of the transistor in which state a drain current is flowing.

A field effect transistor comprising:

• a semiconductor region having one conductivity type and having an impurity concentration,
• a source and a drain both having the same conductivity type as that of said semiconductor region and provided at the opposite ends of said semiconductor region, said drain being adapted to be applied with a drain voltage from an external voltage source to cause a drain current to flow between said drain and said source,
• gates provided at opposite sides of said semiconductor region to define a portion of said semiconductor region and each comprising a ring having a thin thickness in comparison with the diameter thereof, said gates being adapted to be applied with a gate voltage from an external voltage source,
• depletion layers extending from said gates, respectively, inwardly into said portion of said semiconductor region so as to face each other, to define at least one current channel in said portion of said semiconductor region,
• the degree of extension of said depletion layers into said portion of said semiconductor region being controlled by changes in said gate voltage, said channel having predetermined length and width in the absence of any applied gate voltage, said degree of extension of the depletion layers controlling said drain current, thereby defining a transconductance,
• said semiconductor region having a first series resistance between said source and said channel and having a second series resistance through said channel,
• said impurity concentration of said semiconductor region and the length and width of said channel being selected so that the product of said transconductance and the sum of the resistance of said source, said first series resistance and said second series resistance is maintained less that one in the operative state of the transistor in which state a drain current is flowing.

In a junction field effect transistor having a body of n-type semiconductor material which includes a source region at one end and a drain region at an opposite end thereof for conducting current through a channel region which lies along a source-to-drain spacing between said source and drain regions in response to a voltage potential applied between said source and drain regions, and at least one pair of p-type gate regions that are spaced laterally of said channel region and wherein the spacing between each of said gate regions defines lateral dimensions of said channel region, the improvement comprising:

• said gate regions having a gate length L in the direction of said source to drain current flow between the source and drain regions which defines a short channel in said channel region and said gate regions being separated by a lateral spacing "2a" across said channel region wherein said spacing is large relative to said gate length L thereby to further define said short channel in a manner to have a large area that is substantially normal to the direction of current flow between the source and drain regions, and
• said gate length L, gate spacing "2a" and source-to-gate spacing being arranged so that the product R.sub.S .times.G.sub.m <1.0 where R.sub.S is the sum of the resistances from the source to the channel and the resistance of the channel so as to provide triode-like operating characteristics of said junction field effect transistor.