Redundant row fuse bank circuit

An integrated address identification circuit for correlating a plurality of address bits representing an address to a selected bit pattern, each of address bits representing either a first state or a second state, comprising:

• a buffer circuit having an buffer input, the buffer circuit producing at an output terminal a first voltage in response to a voltage above a reference voltage at the buffer input and producing a second voltage in response to a voltage below the reference voltage at the buffer input, the buffer circuit including a signal feedback loop having an output coupled to the buffer input to maintain the buffer input at the first or second voltage;
• a first set of blown fuses, each blown fuse in the first set being coupled between a test node and the reference voltage;
• and
• an isolator circuit coupled between the test node and the buffer input, the isolator circuit having a switching input, the isolator circuit in a closed state electrically connecting the buffer input to the test node and in an open state electrically isolating the test node from the buffer circuit, the isolator being switchable between the closed and open states in response to a predetermined isolation signal at the switching input.

An integrated circuit for detecting a redundant address signal among a set of address signals, comprising:

• a fuse bank including a plurality of fuses, wherein selected ones of the fuses are blown in a pattern corresponding to the redundant address select signal;
• a plurality of fuse select switches coupled to connect or isolate the selected ones of the fuses in a pattern corresponding to the predetermined row address select signal in response to the predetermined row address select signal;
• an isolation circuit switchable in response to an isolation signal between a closed state and an open state, the isolation circuit having an input terminal coupled to the fuse bank and an output terminal, the isolation circuit, in the closed state, transmitting a voltage from the fuse bank to the output terminal, the isolation circuit in an open state blocking current flow from the output terminal to the fuse bank;
• and
• a state storage circuit connected to receive the voltage from the output terminal, the state storage circuit producing a signal indicative of the voltage on the fuse bank being substantially equal to a precharge voltage from a precharge circuit, the state storage circuit further being connected to provide a feedback signal to maintain the precharge voltage on the fuse bank when the precharge circuit does not provide the precharge voltage wherein the isolation circuit in its open state forms an open circuit blocking current flow from the output terminal to the fuse bank.

A method of verifying an address with a fuse bank including a plurality of fuses in an integrated circuit, comprising the steps of:

• providing a test voltage to the fuse bank;
• removing the test voltage from the fuse bank;
• storing a retained voltage across the fuse bank with a storage circuit;
• supplying the stored retained voltage to a memory array;
• after storing the retained voltage across the fuse bank, isolating the fuse bank from the storage circuit with an isolation circuit by blocking current flow from the storage circuit into the isolation circuit;
• and
• after isolating the fuse bank from the storage circuit, maintaining the stored voltage with the storage circuit.