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US 5,583,378 AGranted
Ball grid array integrated circuit package with thermal conductor
AssigneeAmkor Electronics, Inc.
InventorsRobert C. Marrs, Ronald J. Molnar
Life of this patent
Estimating the term…
Abstract
A ball grid array package and low cost method for manufacture of the same is disclosed herein. The ball grid array package includes a thermal conductor which is a linearly co-extensive outer layer of an interconnection substrate and forms the outer surface of the ball grid array package. An integrated circuit chip is positioned on the underside of the package in a well region. The well region is either formed directly in the interconnection substrate or is formed by the application of a dam. The well region is then filled with an insulating encapsulant material to a predetermined level.
Claims40
A packaged integrated circuit device, comprising:
- an interconnection substrate having one layer of conductive trace material and one layer of insulating material formed in or on said interconnection substrate, wherein
- said interconnection substrate has a first surface and a second surface opposite said first surface, said second surface of said interconnection substrate having a plurality of electrical contacts arranged in rows that are electrically connected to said one layer of conductive trace material for making electrical connections from said conductive trace material to contact points external to said packaged integrated circuit device;
- a metallic thermal conductor, said thermal conductor having a first surface attached to said first surface of said interconnection substrate, said thermal conductor having a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, wherein
- a thickness of said thermal conductor between said first surface and said second surface of said thermal conductor is less than 1.0 millimeter, and
- said thermal conductor is linearly co-extensive with said interconnection substrate first surface;
- a well region formed in said interconnection substrate, said well region having a bottom which is an exposed portion of said first surface of said thermal conductor;
- an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached in said well region such that said second surface of said integrated circuit chip and said portion of said first surface of said thermal conductor exposed at said bottom of said well region are adhesively attached;
- and
- a plurality of conductive bond wires, said bond wires making electrical connections between said integrated circuit chip and bonding locations on said one layer of conductive trace material, wherein
- said packaged integrated circuit device has a thickness of less than 2.3 millimeters.
7 more elements
A packaged integrated circuit device, comprising:
- a metallic thermal conductor, said thermal conductor having a first surface and a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, a thickness of said thermal conductor between said first surface and said second surface being less than 1.0 millimeter;
- a first insulating layer, said first insulating layer being applied directly to said first surface of said thermal conductor;
- a first layer of conductive trace material, said first layer of conductive trace material being applied over said first insulating layer;
- an interconnection substrate having one layer of conductive trace material and one layer of insulating material formed in or on said interconnection substrate, wherein
- said interconnection substrate has a first surface and a second surface opposite said first surface, said first surface of said interconnection substrate being attached to said first layer of conductive trace material, said second surface of said interconnection substrate having a plurality of electrical contacts arranged in rows for making electrical connections from said first layer of conductive trace material and said one layer of conductive trace material to contact points external to said packaged integrated circuit device, wherein
- said thermal conductor is linearly co-extensive with said interconnection substrate;
- a well region formed in said interconnection substrate, said well region having a bottom which is an exposed portion of said first conductive trace layer;
- an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached in said well region in a flip-chip configuration such that said first surface of said integrated circuit chip is attached to said exposed portion of said first conductive trace layer at said bottom of said well region, wherein
- said packaged integrated circuit device has a thickness of less than 2.3 millimeters.
6 more elements
A packaged integrated circuit device, comprising:
- a metallic thermal conductor, said thermal conductor having a first surface and a second surface opposite said first surface, which is exposed to the exterior of said packaged integrated circuit device, a thickness of said thermal conductor between said first surface and said second surface being less than 1.0 millimeter;
- a first insulating layer, said first insulating layer being applied directly to said first surface of said thermal conductor;
- a first layer of conductive trace material, said first layer of conductive trace material being applied over said first insulating layer;
- an integrated circuit chip, said integrated circuit chip having a first surface and a second surface opposite said first surface, said integrated circuit chip being attached to a portion of said first conductive trace layer in a flip-chip configuration;
- and
- a dam, said dam being applied to said first layer of conductive trace material such that said dam is positioned around the perimeter of said integrated circuit chip, thereby creating a well region around said integrated circuit chip, wherein
- said packaged integrated circuit device has a thickness of less than 2.3 millimeters.
4 more elements
Dependencies are inferred from the claim text.