Electric motor control chip and method

A circuit for digitizing first and second analog signals for digital processing in a motor control system including a motor and a load driven by the motor, the circuit comprising in combination:

• (a) first and second conductors conducting the first and second analog signals, respectively;
• (b) an analog-to-digital conversion circuit including a CDAC having a charge summing conductor connected to an input of a bit decision comparator;
• (c) a first simultaneous sample and hold MSB circuit coupled between the charge summing conductor and the first conductor, and a second simultaneous sample and hold MSB circuit coupled between the charge summing conductor and the second conductor,
• whereby the first and second analog signals can be simultaneously sampled and held in the first and second simultaneous sample and hold MSB circuits, respectively, and then sequentially converted to digital numbers by the analog-to-digital conversion circuit without resampling of either of the first and second simultaneous sample and hold MSB circuits.

A circuit for digitizing first and second differential analog signals for digital processing in a motor control system including a motor and a load driven by the motor, the circuit comprising in combination:

• (a) first and second conductors conducting the first differential analog signal, and third and fourth conductors conducting the second differential analog signal;
• (b) an analog-to-digital conversion circuit including a main CDAC having a first charge summing conductor and a trim CDAC having a second charge summing conductor;
• (c) a bit decision comparator having a first input coupled to the first charge summing conductor and a second input coupled to the second charge summing conductor;
• (d) first and second differential simultaneous sample and hold MSB circuits,
• the first differential sample and hold MSB circuit including
• i. a first MSB switch circuit connected to a fifth conductor, a first sampling switch connected between the first conductor and the fifth conductor, and a first MSB capacitor having first and second terminals, the first terminal of the first MSB capacitor being connected to the fifth conductor,
• ii. a first isolation switch selectively coupling the second terminal of the first MSB capacitor to the first charge summing conductor during conversion of the first differential analog signal to a digital number,
• iii. a first MSB capacitor grounding switch coupling the second terminal of the first MSB capacitor to a reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• iv. a second MSB switch circuit connected to a sixth conductor, a second sampling switch connected between the second conductor and the sixth conductor, and a second MSB capacitor having first and second terminals, the first terminal of the second MSB capacitor being connected to the sixth conductor,
• v. a second isolation switch selectively coupling the second terminal of the second MSB capacitor to the second charge summing conductor during conversion of the first differential analog signal to a digital number,
• vi. a second MSB capacitor grounding switch coupling the second terminal of the second MSB capacitor to the reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• the second differential simultaneous sample and hold MSB circuit including
• vii. a third MSB switch circuit connected to a seventh conductor, a third sampling switch connected between the third conductor and the seventh conductor, and a third MSB capacitor having first and second terminals, the first terminal of the third MSB capacitor being connected to the seventh conductor,
• viii. a third isolation switch selectively coupling the second terminal of the third MSB capacitor to the first charge summing conductor during conversion of the second differential analog signal to a digital number,
• ix. a third MSB capacitor grounding switch coupling the second terminal of the third MSB capacitor to the reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• x. a fourth MSB switch circuit connected to an eighth conductor, a fourth sampling switch connected between the fourth conductor and the eighth conductor, and a fourth MSB capacitor having first and second terminals, the first terminal of the fourth MSB capacitor being connected to the eighth conductor,
• xi. a fourth isolation switch selectively coupling the second terminal of the fourth MSB capacitor to the second charge summing conductor during conversion of the second differential analog signal to a digital number, and
• xii. a fourth MSB capacitor grounding switch coupling the second terminal of the fourth MSB capacitor to the reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• whereby the first and second differential analog signals can be simultaneously sampled and held in the first and second differential simultaneous sample and hold MSB circuits, respectively, and then sequentially converted to digital numbers by the analog-to-digital conversion circuit.

An analog-to-digital converter for digitizing first and second analog signals, comprising in combination:

• (a) first and second conductors conducting the first and second analog signals, respectively;
• (b) a single analog-to-digital conversion circuit including a single CDAC having a charge summing conductor connected to an input of a bit decision comparator;
• (c) a first simultaneous sample and hold MSB circuit coupled between the charge summing conductor and the first conductor, and a second simultaneous sample and hold MSB circuit coupled between the charge summing conductor and the second conductor,
• whereby the first and second analog signals can be simultaneously sampled and held in the first and second sample and hold MSB circuits, respectively, and then sequentially converted to digital numbers by the analog-to-digital conversion circuit.

An analog-to-digital converter circuit for digitizing first and second differential analog signals, comprising in combination:

• (a) first and second conductors conducting the first differential analog signal, and third and fourth conductors conducting the second differential analog signal;
• (b) an analog-to-digital conversion circuit including a main CDAC having a first charge summing conductor and a trim CDAC having a second charge summing conductor;
• (c) a bit decision comparator having a first input coupled to the first charge summing conductor and a second input coupled to the second charge summing conductor;
• (d) first and second differential simultaneous sample and hold MSB circuits,
• the first differential sample and hold MSB circuit including
• i. a first MSB switch circuit connected to a fifth conductor, a first sampling switch connected between the first conductor and the fifth conductor, and a first MSB capacitor having first and second terminals, the first terminal of the first MSB capacitor being connected to the fifth conductor,
• ii. a first isolation switch selectively coupling the second terminal of the first MSB capacitor to the first charge summing conductor during conversion of the first differential analog signal to a digital number,
• iii. a first MSB capacitor grounding switch coupling the second terminal of the first MSB capacitor to a reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• iv. a second MSB switch circuit connected to a sixth conductor, a second sampling switch connected between the second conductor and the sixth conductor, and a second MSB capacitor having first and second terminals, the first terminal of the second MSB capacitor being connected to the sixth conductor,
• v. a second isolation switch selectively coupling the second terminal of the second MSB capacitor to the second charge summing conductor during conversion of the first differential analog signal to a digital number,
• vi. a second MSB capacitor grounding switch coupling the second terminal of the second MSB capacitor to the reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• the second differential simultaneous sample and hold MSB circuit including
• vii. a third MSB switch circuit connected to a seventh conductor, a third sampling switch connected between the third conductor and the seventh conductor, and a third MSB capacitor having first and second terminals, the first terminal of the third MSB capacitor being connected to the seventh conductor,
• viii. a third isolation switch selectively coupling the second terminal of the third MSB capacitor to the first charge summing conductor during conversion of the second differential analog signal to a digital number,
• ix. a third MSB capacitor grounding switch coupling the second terminal of the third MSB capacitor to the reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• x. a fourth MSB switch circuit connected to an eighth conductor, a fourth sampling switch connected between the fourth conductor and the eighth conductor, and a fourth MSB capacitor having first and second terminals, the first terminal of the fourth MSB capacitor being connected to the eighth conductor,
• xi. a fourth isolation switch selectively coupling the second terminal of the fourth MSB capacitor to the second charge summing conductor during conversion of the second differential analog signal to a digital number, and
• xii. a fourth MSB capacitor grounding switch coupling the second terminal of the fourth MSB capacitor to the reference voltage during simultaneous sampling of the first and second differential simultaneous sample and hold MSB circuits,
• whereby the first and second differential analog signals can be simultaneously sampled and held in the first and second differential simultaneous sample and hold MSB circuits, respectively, and then sequentially converted to digital numbers by the analog-to-digital conversion circuit.

A control system for controlling a motor coupled to drive a load, the load including a load position indicating device producing a first analog signal indicative of load shaft position or speed, the motor including a motor position indicating device producing a second analog signal indicative of motor position or speed, the motor receiving a plurality of pulse width modulated primary winding currents from a plurality of power switches, respectively, the control system comprising in combination:

• (a) a microcontroller applying a plurality of pulse width modulated control signals to the power switches, respectively, and also producing a clock signal and a conversion signal;
• (b) a plurality of current sensing devices coupled to the motor and producing a plurality of primary winding current indicating signals representative of the primary winding currents, respectively;
• (c) a conversion circuit receiving the clock signal, the conversion signal, the first and second analog signals, and the primary winding current indicating signals and digitizing the first and second analog signals and the primary winding current indicating signals, the conversion circuit including
• i. first and second conductors conducting first and second analog signals, respectively;
• ii. an analog-to-digital converter circuit including a CDAC having a first charge summing conductor connected to a first input of a bit decision comparator;
• iii. the first simultaneous sample and hold MSB circuit coupled between the first charge summing conductor and the first conductor, and a second simultaneous sample and hold MSB circuit coupled between the first charge summing conductor and the second conductor,
• whereby the first and second analog signals can be simultaneously sampled and held in the first and second sample and hold MSB circuits, respectively, then sequentially converted to digital numbers by the analog-to-digital converter circuit, and then utilized by the microcontroller to adjust the pulse width modulated control signals.

A system for digitizing a differential analog input signal, comprising in combination:

• (a) first and second conductors conducting the differential analog input signal;
• (b) an analog-to-digital converter including a CDAC having differential sample and hold circuitry coupled to receive a differential analog input signal from the first and second conductors and operatively coupled to sample and hold the differential input signal, the CDAC including first and second charge summing conductors coupled both to the differential sample and hold circuitry and to first and second inputs of a bit decision comparator, respectively;
• (c) a main reference voltage conductor connected to the CDAC;
• (d) a programmable reference voltage generating circuit including
• i. a reference circuit producing a first reference voltage on a first reference voltage conductor,
• ii. a first unity gain buffer circuit receiving the first reference voltage and producing a buffered second reference voltage on a second reference voltage conductor,
• iii. a resistive divider circuit coupled to receive the buffered second reference voltage and producing a plurality of divided-down reference voltages on a plurality of junction node conductors, respectively, of the resistive divider circuit,
• iv. a plurality of switches coupled between the main reference voltage conductor and the junction node conductors and responsive to a plurality of reference voltage selection signals, respectively, for selectively applying the divided-down reference voltages to the main reference voltage conductor to thereby apply a selected reference voltage to the CDAC,
• whereby (1) noise generated by the first unity gain buffer circuit is divided down by the resistive divider circuit by the same ratio as the buffered second reference voltage so a noise-to-reference voltage ratio of the selected reference voltage is not reduced for lower values of the selected reference voltage, and (2) common mode noise on the first and second conductors is rejected by the bit decision comparator.

A method for accurately digitizing a first differential analog signal in a high electrical noise environment by means of an analog-to-digital converter including a main CDAC coupled to a first charge summing conductor coupled to an input of a bit decision comparator and a trim CDAC coupled to a second charge summing conductor which is coupled to another input of the bit decision comparator, an output of the bit decision comparator being coupled to an input of a successive approximation register, the method comprising the steps of:

• (a) conducting the first differential analog signal along a first pair of conductors to apply the first differential analog signal between an input of a first sample and hold MSB circuit in the first main CDAC and another input of a second sample and hold MSB circuit in the first trim CDAC;
• (b) sampling and holding the voltages on the inputs of the first and second sample and hold MSB circuits, respectively, by charging up MSB capacitors in each of the first and second sample and hold MSB circuits to voltage levels representative of the voltages on the inputs of the first and second sample and hold MSB circuits, respectively;
• (c) performing a plurality of charge distribution operations between (i) the MSB capacitor in the first sample and hold MSB circuit and bit capacitors coupled to the first charge summing conductor and (ii) the MSB capacitor in the second sample and hold MSB circuit and bit capacitors coupled to the second charge summing conductor, in accordance with bit signal outputs produced by the successive approximation register;
• (d) applying voltages on the first and second charge summing conductors as a result of step (c) to the inputs of the bit decision comparator, respectively,
• whereby common mode noise produced on the first and second conductors by the high electrical noise environment is substantially rejected by the bit decision comparator and therefore does not result in substantial bit decision errors.