FET and/or bipolar devices formed in thin vertical silicon on insulator (SOI) structures

A semiconductor structure containing integrated circuits comprising:

• a plurality of silicon vertical sidewalls formed as sections of a multisectioned cell, each silicon vertical sidewall being of predetermined thickness and having top, bottom, and substantially vertical front and back silicon surfaces, said silicon sidewalls containing impurity regions of semiconductor devices, said impurity regions being stacked vertically on top of one another in layered planes, each said impurity region contacted electrically at one of said front, back and top surfaces, and wherein said at least one pair of sidewalls having an interconnection between corresponding impurity regions of two semiconductor devices made in a layered plane of said corresponding impurity regions;
• and
• an insulating layer in contact with the bottom surface of said silicon sidewalls;
• and
• an insulating barrier covering said top and vertical front and back surfaces of the silicon sidewall except where electrical contacts to said impurity regions are located.