Tunable operational transconductance amplifier and two-quadrant multiplier employing MOS transistors

A tunable MOS operational transconductance amplifier which outputs a differential output current in response to a differential input voltage, comprising:

• a first tail current source;
• a second tail current source;
• first and second transistor pairs having drains cross-coupled to each other and having sources connected commonly to said first tail current source;
• and
• a differential pair constituted from transistors connected in cascode and connected to said second tail current source;
• gates of transistors on upper stage side constituting said differential pair being connected in common to be applied a tuning voltage thereto, sources of said transistors on the upper stage side being connected to the gates of said first transistor pair, respectively, gates of transistors on lower stage side which constitute said differential pair being connected to gates of said second transistor pair, respectively.

A tunable MOS two-quadrant multiplier which outputs a differential output current in response to the product of values of two input voltages, comprising:

• first and second transistor pairs having sources grounded commonly;
• and
• a third transistor pair connected in cascode to said first transistor pair and serving as loads to said first transistor pair;
• gates of said second transistor pair being individually connected to drains of said first transistor pair;
• a differential input voltage being applied as a first input voltage between gates of said third transistor pair, a second input voltage being applied to gates of said first transistor pair which are connected commonly, the differential output current including at least drain currents of said second transistor pair.

A tunable MOS two-quadrant multiplier which outputs a differential output current in response to the product of values of two input voltages, comprising:

• first and second transistor pairs having sources grounded commonly;
• and
• a third transistor pair connected in cascode to said first transistor pair and serving as loads to said first transistor pair;
• drains of said second transistor pair being connected not in cross-coupling to drains of said third transistor pair;
• gates of said second transistor pair being individually connected to drains of said first transistor pair;
• a differential input voltage being applied as a first input voltage between gates of said first transistor pair, a second input voltage being applied to gates of said third transistor pair which are connected commonly, the differential output current including at least drain currents of said second transistor pair.