Voltage compensating CMOS input buffer circuit

A supply voltage compensating input buffer circuit, comprising:

• an input inverter having complimentary p-channel and n-channel transistors coupled in series between the supply voltage and a reference voltage, said input inverter receiving an input signal and switching its output state based on predetermined high and low trip point levels of the input signal;
• a voltage compensating circuit coupled to the output of the input inverter for providing a supply voltage variable active load to at least one of the p-channel and n-channel transistors to stabilize the levels of input signals at which the input inverter switches its output state when the supply voltage changes, wherein the voltage compensating circuit comprises:
• a voltage compensating transistor coupled in series between the output of the input inverter and the reference voltage;
• and
• a pair of trip point centering transistors coupled in series with the voltage compensating transistor between the output of the input inverter and the reference voltage.

A supply voltage compensating CMOS input buffer circuit, comprising:

• an input inverter for receiving an input signal, having pairs of complimentary p-channel and n-channel transistors coupled in series between the supply voltage and a reference voltage, said transistors having a channel size ratio selected to provide TTL input trip points at a predetermined supply voltage and switching logic levels of an output based on the level of the input signal reaching said trip points;
• a voltage compensating n-channel transistor coupled to the output of the input inverter for providing a supply voltage variable active load to the p-channel transistors to stabilize the levels of input signals at which the input inverter switches its output state when the supply voltage changes;
• a pair of n-channel transistors coupled in series with the voltage compensating transistor, one on either side thereof, having gates coupled to the input signal;
• a voltage adjusting circuit, comprising;
• an n-channel transistor having a gate coupled to the supply voltage, and its drain coupled to the gate of the voltage compensating transistor;
• a pair of diodes coupled in series between the supply voltage and the gate of the voltage compensating transistor;
• and
• an output inverter coupled to the output of the input inverter for inverting the output of the input inverter to provide CMOS logic levels.