Method and apparatus for configurable build-in self-repairing of ASIC memories design

A process for on-chip testing and repairing configurable ASIC memories in a system that contains a test circuit, a repair circuit, a memory array, and a plurality of redundant lines within the memory array, the test circuit including a test pattern generator, the process comprising the steps of:

• supplying a test pattern by the test pattern generator for testing a plurality of memory cells in the memory array;
• detecting at least one fault in the memory array by the test circuit;
• transferring the original address location of the at least one faulty line from the test circuit to the repair circuit;
• storing an original address location of the at least one faulty memory line;
• translating the original address location of the at least one faulty line to a mapped address location of at least one redundant line:
• and
• redirecting the original address location of the at least one faulty line to the mapped address location of the at least one redundant line.

An on-chip system for testing and repairing faulty ASIC memories comprising:

• a memory array including a matrix of memory cells formed by intersecting a plurality of column lines with a plurality of row lines;
• a redundant line, coupled to the memory array, for replacing faulty lines;
• a testing circuit, coupled to the memory array, for testing the memory array and determining an original address of a line in the memory array that includes a fault;
• and
• a repair circuit, coupled to the memory array and the testing circuit, for repairing the faulty line with a redundant line by redirecting the original address to an address of the redundant line.