Telecommunications switch architecture

A switching architecture, including a plurality of incoming links and a plurality of outgoing links, and switch means for switching data between the incoming and outgoing links, which data is in serial form on said incoming links, the architecture further including means for convening said serial data into parallel form and comprising, for each incoming link, address decode and memory write means;

• one or more input memory blocks in which said data is stored at specific addresses;
• means for replicating the data whereby all incoming data are available for all or selected outgoing links, said converting, storing and replicating means being interconnected whereby the storage occurs before the replication or concurrently therewith and the replication occurs when the data is in serial or parallel form;
• means for each replication, for transferring data from one of said memory blocks to the appropriate one of said outgoing links, which transfer means is arranged either to read directly from the relevant address in said input memory blocks or to transfer the content of all or part of said input memory blocks simultaneously en bloc and in parallel to a plurality of output memory blocks, each associated with a respective outgoing link;
• and means for each outgoing link for taking the incoming data intended therefor and reading that data out in serial form, wherein there is a respective source memory for each incoming link, the decoded address information being stored in a respective area of the source memory, each of which source memories comprises a said input memory block, wherein means are provided to convert the source memory content to optical form and the replicating means comprises optical replicating means for acting on said optical form of the source memory content, there being a respective destination memory for each said outgoing link, each of which destination memories comprises a said output memory block, a respective read-out means being connected to each said destination memory, each outgoing link being connected to a respective read-out means and the read-out means serving only to read out the memory content intended for that outgoing link as determined from said stored address information, and including central or distributed control means controlling the operation of the address decode and memory write means, the source memories, the destination memories and the read-out means.