Video decoder

A digital signal decoder system for receiving encoded digitized video signals and transmitting decoded digital video signals, said decoder system having a RAM with (1) a compressed, encoded Data Buffer adapted to receive and store encoded compressed digital video data, and (2) a data portion for storing decompressed digital video buffer, a Memory Management Unit for managing the RAM, and an integrated circuit chip comprising:

• a. a FIFO Data Buffer;
• b. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof;
• c. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation:
• C"=(U NAND V) NAND ((U XOR V) NAND ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z))),
• C'=(U XOR V ) XOR ((x NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and
• S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3)parallel counter and C', C", S are outputs of the (2,3,3) parallel counter,
• for dequantizing the decoded data from the variable length decoder;
• d. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;
• e. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;
• f. a Display Unit to output motion compensated pictures from the RAM;
• and
• g. a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

An integrated circuit chip for a system for receiving encoded digitized video signals and transmitting decoded digital video signals, said system including the integrated circuit chip and a RAM with (1) a compressed, encoded Data Buffer adapted to receive and store encoded compressed digital video data, and (2) a data portion for storing decompressed digital video buffer, a Memory Management Unit for managing the RAM, the integrated circuit chip comprising:

• a. a FIFO Data Buffer;
• b. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof;
• c. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation:
• C"=(U AND V) NAND ((U XOR V) NAND ((X AND Y) NAND (X NAND Z) NAND (Y NAND Z))),
• C'=(U XOR V) XOR ((X AND Y) NAND (X NAND Z) NAND (Y NAND Z)), and
• S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3) parallel counter and C', C", S are outputs of the (2,3,3) parallel counter,
• for dequantizing the decoded data from the variable length decoder;
• d. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;
• e. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;
• f. a Display Unit to output motion compensated pictures from the RAM;
• and
• g. a reduced instruction set Controller to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit.

A digital entertainment system comprising a digital signal decoder system for receiving encoded digitized video signals and transmitting decoded digital video signals, said decoder system comprising:

• a. a FIFO Data Buffer;
• b. a RAM having (1) a compressed, encoded Data Buffer connected to the FIFO Data Buffer and adapted to receive and store encoded compressed digital video data therefrom, and (2) a data portion for storing decompressed digital video buffer;
• c. a Memory Management Unit for managing the RAM;
• d. a Variable Length Code Decoder for receiving encoded data from the RAM compressed, encoded Data Buffer, and providing a decoded bit stream thereof;
• e. a (2,3,3) parallel counter Inverse Quantizer having the Boolean representation:
• C"=(U NAND V) NAND ((U XOR V) NAND ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z))),
• C'=(U XOR V) XOR ((X NAND Y) NAND (X NAND Z) NAND (Y NAND Z)), and
• S=(X XOR Y) XOR Z, where U, V, X, Y, and Z are inputs to the (2,3,3) parallel counter and C', C", S are outputs of the (2,3,3) parallel counter,
• for dequantizing the decoded data from the variable length decoder;
• f. an Inverse Discrete Cosine Transform Decoder for inverting the dequantized, decoded data into Intrapictures, Predicted Pictures, and Bidirectional predicted Pictures;
• g. a Motion Compensator for receiving Intrapictures and other information from the RAM, and error functions, and forming motion compensated predicted pictures therefrom for return to the RAM;
• h. a Display Unit to output motion compensated pictures from the RAM;
• i. a reduced instruction set Controller to determine the state of the FIFO Data Buffer and to control the Memory Management Unit, the Variable Length Code Decoder, the Inverse Quantizer, the Inverse Discrete Cosine Transform Decoder, the Motion Compensator, and the Display Unit;
• j. an audio decoder unit;
• and
• k. an output unit chosen from a television set, a recorder, a computer, and a network for rebroadcast.