Thin film semiconductor device with gate metal oxide and sidewall spacer

A semiconductor device comprising:

• a substrate having an insulating surface;
• and
• a plurality of thin film transistors formed on said insulating surface, at least one of said thin film transistors comprising a silicon semiconductor layer including source, drain and channel regions, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode wherein said source and drain regions are offset from said gate electrode by a thickness of said oxide insulating layer
• wherein said at least one of the thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

A monolithic circuit comprising:

• a substrate having an insulating surface, said substrate including an active matrix circuit portion and a peripheral circuit portion;
• a first plurality of thin film transistors formed on the active matrix circuit portion of the substrate, each of said first plurality of thin film transistors having at least silicon semiconductor layer including source, drain and channel regions therein, an insulated gate electrode formed on said channel region, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode;
• and
• a second plurality of thin film transistors formed on the peripheral circuit portion of the substrate for driving said first plurality of thin film transistors, each of said second plurality of thin film transistors having at least silicon semiconductor layer including source, drain and channel regions therein, and an insulated gate electrode adjacent to said channel region,
• wherein only said first plurality of thin film transistors are provided with metal silicide regions on or in contact with the source and drain regions thereof, and each of said first plurality of thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

A monolithic circuit comprising:

• a substrate having an insulating surface, said substrate including an active matrix circuit portion and a peripheral circuit portion;
• a first plurality of thin film transistors formed on the active matrix circuit portion of the substrate;
• and
• a second plurality of thin film transistors formed on the peripheral circuit portion of the substrate for driving said first plurality of thin film transistors, wherein (a) each of said first and second plurality of thin film transistors comprises a silicon semiconductor layer including source, drain and channel regions therein, metal silicide regions connected to said source and drain regions, a gate insulating layer formed on said semiconductor layer, and a gate electrode formed on said gate insulating layer and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode;
• (b) each of said first and second plurality of thin film transistors is provided with side spacers formed adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween;
• and (c) inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.

A semiconductor device comprising:

• a substrate having an insulating surface;
• a pair of p-channel thin film transistor and an n-channel thin film transistor formed on said insulating surface;
• each of said p-channel and n-channel thin film transistors having a pair of impurity silicon semiconductor regions, a channel semiconductor region extending therebetween, metal silicide regions connected to said impurity silicon semiconductor regions, a gate insulating layer formed on said channel semiconductor region, a gate electrode formed on said gate insulating layer, and an oxide insulating layer comprising an oxide of a material of said gate electrode formed on at least side surfaces of said gate electrode;
• and
• one of the pair of impurity regions of said p-channel thin film transistor being electrically connected with one of the pair of impurity regions of said n-channel thin film transistors through corresponding one of said metal silicide regions formed therebetween,
• wherein said each of said p-channel and n-channel thin film transistors is provided with side spacers adjacent to the side surfaces of said gate electrode with said oxide insulating layer interposed therebetween, and inner edges of said metal silicide regions are substantially aligned with outer edges of said side spacers.