Polishing pad cluster for polishing a semiconductor wafer

A polishing pad cluster for polishing a semiconductor wafer comprising a plurality of integrated circuit dies, said cluster comprising:

• a pad support;
• a plurality of polishing pads, each pad having a polishing area substantially smaller than the wafer and substantially the same area as an individual one of the integrated circuit dies;
• and
• a plurality of polishing pad mounts, each mount isolated from at least one adjacent mount, coupled to a respective one of the polishing pads, and supported by the support, each mount comprising a respective joint comprising at least two degrees of freedom to allow the associated polishing pad to articulate with respect to the support to conform to the wafer.

A polishing pad cluster for polishing a semiconductor wafer comprising a plurality of integrated circuit dies, said cluster comprising:

• a pad support;
• a plurality of polishing pads, each pad having a polishing area substantially smaller than the wafer and not substantially smaller than an individual one of the integrated circuit dies;
• and
• a plurality of polishing pad mounts, each mount coupled to a respective one of the polishing pads and supported by the support, each mount comprising a respective joint comprising at least two degrees of freedom to allow the associated polishing pad to articulate with respect to the support to conform to the wafer, each mount being substantially rigid in a direction perpendicular to the respective pad toward the pad support;
• wherein the joints are formed by a layer of a substantially incompressible material supported rigidly by the pad support against movement away from the wafer.

A polishing pad cluster for polishing a semiconductor wafer comprising a plurality of integrated circuit dies, said cluster comprising:

• a pad support;
• a plurality of polishing pads, each pad having a polishing area substantially smaller than the wafer and not substantially smaller than an individual one of the integrated circuit dies;
• and
• a plurality of polishing pad mounts, each mount coupled to a respective one of the polishing pads and supported by the support, each mount comprising a respective joint comprising at least two degrees of freedom to allow the associated polishing pad to articulate with respect to the support to conform to the wafer, each mount being substantially rigid in a direction perpendicular to the respective pad toward the pad support;
• at least one magnet, the semiconductor wafer positioned between the magnet and the polishing pads, at least some of said joints and said polishing pads comprising ferromagnetic material such that the magnet biases the polishing pads against the wafer.

A polishing pad assembly for polishing a semiconductor wafer, said assembly comprising:

• a semiconductor wafer;
• at least one polishing pad supported on a ferromagnetic element;
• and
• at least one magnet;
• said wafer positioned between the pad and the magnet such that magnetic forces produced by the magnet on the ferromagnetic element bias the pad against the wafer.

A polishing pad cluster for polishing a semiconductor wafer comprising a plurality of integrated circuit dies, said cluster comprising:

• a pad support;
• a plurality of polishing pads, each pad having a polishing area substantially smaller than the wafer and not substantially smaller than an individual one of the integrated circuit dies;
• and
• a plurality of polishing pad mounts, each mount isolated from at least one adjacent mount, coupled to a respective one of the polishing pads, and supported by the support, each mount comprising a respective joint comprising at least two degrees of freedom to allow the associated polishing pad to articulate with respect to the support to conform to the wafer;
• at least one magnet, the semiconductor wafer positioned between the magnet and the polishing pads, at least some of said joints and said polishing pads comprising ferromagnetic material such that the magnet biases the polishing pads against the wafer.