Multiprocessor coupling system with integrated compile and run time scheduling for parallelism

A very long instruction word parallel data processing system comprising:

• a plurality of processing units;
• and
• memory having stored therein sequential multiple-operation instruction words for each of plural threads of computation, each instruction word comprising plural fields, each field identifying an operation for a respective one of the plurality of processing units such that all operations identified by a multiple operations instruction word may be executed simultaneously on respective processing units with processing of a single thread;
• each processing unit comprising a synchronizer for selecting one of plural threads of computation for execution in that unit, the unit then executing the operation identified in the respective field of a next instruction word for the selected thread of computation, the synchronizer allowing parallel units to simultaneously execute operations from different thread instruction words such that execution of multiple-operation instruction words for plural threads is interleaved across the plural units;
• wherein the processing units are grouped in clusters with instruction words spanning the clusters, each cluster of processing units sharing a register file for plural threads of computation which is separate from register files of other clusters for the same threads of computation such that the processing units of each cluster read from the register file of only that cluster, the system further comprising means for writing from a processing unit of one cluster to the register file of another cluster.

A very long instruction word parallel data processing system comprising:

• a plurality of processing units grouped in clusters with instruction words spanning the clusters, each cluster of at least one processing unit sharing a register file for plural threads of computation which is separate from register files of other clusters for the same threads of computation such that the processing units of each cluster read from the register file of only that cluster, the system further comprising means for writing from a processing unit of one cluster to the register file of another cluster;
• and
• memory having stored therein sequential multiple-operation instruction words for each of plural threads of computation, each instruction word comprising plural fields spanning the clusters, each field identifying an operation for a respective one of the plurality of processing units such that all operations identified by a multiple operation instruction word may be executed simultaneously on respective processing units with processing of a single thread;
• each processing unit comprising a processing pipeline including:
• a read register stage for reading operands from a register file and supplying those operands to an operation buffer for each of plural threads of computation prior to execution;
• a synchronization stage following the read register stage for selecting one of plural threads of computation for that processing unit and issuing the operation identified in the respective field of a next instruction word for the selected thread of computation, the synchronizer stage allowing parallel units to simultaneously issue operations from different thread instruction words such that issuance of multiple-operation instruction words for plural threads are interleaved across the plural units;
• and
• an execution stage for executing operations issued by the synchronizer stage.

A method of very long instruction word parallel processing comprising:

• providing plural sequences of multiple operation instruction words, each sequence being for a thread of computation and each instruction word comprising fields for identifying plural operations able to be performed in parallel for the respective thread of computation such that all operations identified by a multiple operation instruction word may be executed simultaneously on respective processing units with processing of a single thread;
• and
• processing operations of plural threads of computation in shared parallel processors such that, in a processing cycle, the parallel processors may execute operations from a common instruction word in parallel and may process operations from different instruction words of different threads of computation such that execution of threads is interleaved across the plural processors;
• wherein the operations are processed in parallel processor pipelines, the method comprising reading operands from a register file, supplying those operands to an operation buffer, and selecting an operation from the operation buffer for execution, the step of selecting being by a synchronizer which allows parallel units to simultaneously execute operations from different thread instruction words, the operation buffer storing operations with operand data for each of plural threads of computation prior to execution, the synchronizer stage dynamically selecting an operation for execution after its operands have been stored in the operation buffer.