US 5,574,457 AGranted

Switched capacitor gain stage

AssigneeMotorola, Inc.

InventorsDouglas A. Garrity, Patrick L. Rakers

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Abstract

A switched capacitor gain stage (21) that samples an input voltage every clock cycle phase for effectively doubling the frequency of operation. The switched capacitor gain stage (21) comprising an amplifier (22), a first capacitor network, and a second capacitor network. Either the first or second capacitor network is sampling an input voltage. For example, the first capacitor network samples an input voltage. Capacitors of the first capacitor network are coupled to sample the input voltage via switches. Capacitors of the second switched capacitor network are coupled around the amplifier (22) in a gain configuration via switches. The capacitors of the second switched capacitor network having a voltage stored from a previous clock phase. In a next clock phase the second switched capacitor network are coupled via switches for sampling an input voltage and the first switched capacitor network is coupled via switches in a gain configuration around the amplifier (22).

Claims22

Dependent claims

A switched capacitor gain stage having an input and an output, the switched capacitor gain stage comprising:

an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output coupled to the output of the switched capacitor gain stage;
a first capacitor having a first terminal and a second terminal;
a first switch having a first terminal coupled to said first terminal of said first capacitor and a second terminal coupled to said output of said amplifier;
a second switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal coupled said first terminal of said first capacitor;
a third switch having a first terminal coupled to said second terminal of said first capacitor and a second terminal coupled to said inverting input of said amplifier;
a fourth switch having a first terminal coupled to said second terminal of said first capacitor and a second terminal coupled to said power supply terminal;
a fifth switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal;
a second capacitor having a first terminal coupled to said second terminal of said fifth switch and a second terminal coupled to said second terminal of said first capacitor;
a third capacitor having a first terminal and a second terminal;
a sixth switch having a first terminal coupled to said first terminal of said third capacitor and a second terminal coupled to said output of said amplifier;
a seventh switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal coupled said first terminal of said third capacitor;
an eighth switch having a first terminal coupled to said second terminal of said third capacitor and a second terminal coupled to said inverting input of said amplifier;
a ninth switch having a first terminal coupled to said second terminal of said third capacitor and a second terminal coupled to said power supply terminal;
a tenth switch having a first terminal coupled to the input of the switched capacitor gain stage and a second terminal;
and
a fourth capacitor having a first terminal coupled to said second terminal of said tenth switch and a second terminal coupled to said second terminal of said third capacitor.

13 more elements

A clocked gain stage having an input and an output comprising:

an amplifier having an inverting input, a non-inverting input coupled to a power supply terminal, and an output coupled to the output of the clocked gain stage;
a first capacitor;
a second capacitor, said first and second capacitor being coupled between the input of the clocked gain stage and said power supply terminal during a first phase of a clock cycle for sampling a voltage of an input signal applied to the input of the clocked gain stage and said first and second capacitor being coupled in a gain configuration around said amplifier during a second phase of said clock cycle for amplifying a voltage sampled during said first phase of said clock cycle;
a third capacitor;
and
a fourth capacitor, said third and fourth capacitor being coupled between the input of the clocked gain stage and said power supply terminal during said second phase of said clock cycle for sampling a voltage of said input signal applied to the input of the clocked gain stage and said third and fourth capacitors being coupled in a gain configuration around said amplifier during a first phase of a clock cycle for amplifying a voltage sampled during a second phase of a previous clock cycle.

3 more elements

A pipelined Analog to Digital Converter (ADC) including a plurality of series coupled switched capacitor gain stages, the pipelined ADC wherein at least one switched capacitor gain stage of said plurality of series coupled switched capacitor gain stages samples and amplifies a voltage during both clock phases of a clock signal for increasing an operating speed of the pipelined ADC.

Dependencies are inferred from the claim text.