System for generating floating point test vectors
AssigneeAdvanced Micro Devices, Inc.
InventorNorman Bujanos
Life of this patent
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Abstract
A test-vector generating system (200) controls a processor (110) having a paradigm floating point functional unit (160) which executes a paradigm floating point instruction set. The system includes computer program modules including an interactive test selection process (202) in which a test instruction is selected from the paradigm instruction set, an operand data generation process (222), a test instruction execution process (226) in which the paradigm functional unit executes the test instruction operating upon the generated operand data and a test vector result recording process (208) in which a test vector result of the test instruction execution is recorded.
Claims45
A method of generating a test vector, comprising the steps of:
- providing a design functional unit which is designed to emulate a paradigm functional unit;
- executing a plurality of program instructions on a processor which includes a fabricated circuit form of the paradigm functional unit, the program instructions including a plurality of instructions in a paradigm instruction set executed by the paradigm functional unit;
- selecting a test instruction of the paradigm instruction set;
- generating operand data which is operated upon by the paradigm functional unit executing the test instruction;
- executing the test instruction operating upon the generated data;
- accessing a storage stored by the fabricated circuit form of the paradigm functional unit within the processor to retrieve a test vector result;
- and
- recording a test vector result of the test instruction execution for testing the design functional unit.
A method of generating a test vector, comprising the steps of:
- providing a design functional unit which is designed to emulate a paradigm functional unit;
- executing a plurality of program instructions on a processor which includes a fabricated circuit form of the paradigm floating point functional unit, the program instructions including a paradigm floating point instruction set executed by the paradigm floating point functional unit;
- selecting a test instruction of the paradigm floating point instruction set;
- generating operand data which is operated upon by the paradigm floating point functional unit executing the test instruction;
- executing the test instruction operating upon the generated data;
- accessing a storage stored by the fabricated circuit form of the paradigm functional unit within the processor to retrieve a test vector result;
- and
- recording a test vector result of the test instruction execution for testing the design functional unit.
A computer program for generating test vectors for testing a design functional unit which is designed to emulate a paradigm functional unit, the computer program controlling a processor having a fabricated circuit form of the paradigm functional unit which executes a paradigm instruction set, the system including an arrangement of instructions formed into a plurality of modules comprising:
- an interactive test selection process in which a test instruction is selected from the paradigm instruction set, the test instruction testing the design functional unit which is designed to emulate the paradigm functional unit;
- an operand data generation process;
- a test instruction execution process in which the fabricated circuit form of the paradigm functional unit executes the test instruction operating upon the generated operand data;
- and
- a test vector result recording process in which a test vector result of the test instruction execution is recorded.
A test-vector generating system for generating test vectors for testing a design functional unit which is designed to emulate a paradigm functional unit, the system comprising:
- a processor;
- a fabricated circuit form of the paradigm functional unit coupled to the processor and operable to execute a paradigm instruction set;
- and
- a computer program system having an arrangement of instructions formed into a plurality of modules including:
- an interactive test selection process in which a test instruction is selected from the paradigm instruction set, the test instruction testing the design functional unit which is designed to emulate the paradigm functional unit;
- an operand data generation process;
- a test instruction execution process in which the fabricated circuit form of the paradigm functional unit executes the test instruction operating upon the generated operand data;
- and
- a test vector result recording process in which a test vector result of the test instruction execution is recorded.
Dependencies are inferred from the claim text.