Convolutional interleaver and deinterleaver

A method of convolutionally interleaving or deinterleaving a stream of data bytes comprising:

• repeatedly developing a first predetermined sequence of numbers;
• developing a second sequence of numbers, at a lower rate, extending from a first number to a second number;
• combining each number of said second sequence of numbers with each of the numbers of said first sequence of numbers to generate a sequence of addresses to address memory locations;
• reading the stored data byte at each addressed memory location;
• and
• writing a new data byte to the same addressed memory location.

A circuit for convolutionally interleaving or deinterleaving a stream of data bytes comprising:

• first number generating means for repeatedly developing a first predetermined sequence of B numbers, where B is related to a selected interleave depth of said stream of data bytes;
• second number generating means for developing a second sequence of ((B-1)N/2)+1 numbers at a slower rate and extending from a first number to a second number, where N is related to a selected error correction block size of said stream of data
• combining means for combining each number of said second sequence of numbers with each of the numbers of said first sequence of numbers and producing an output;
• a memory for storing data bytes;
• means for supplying said stream of data bytes to said memory;
• and
• means for sequentially addressing memory locations in said memory under control of said output to read a data byte from said addressed location and to write a data byte to the same addressed location.

A circuit for convolutionally interleaving or deinterleaving a data stream comprising successive equal length blocks of R-S encoded data bytes, said circuit comprising:

• a divide-by-B counter responsive to a byte clock signal for generating an output count, where B is a selected interleave depth;
• means for multiplying said output count by the factor N/B, where N is a value equal to or greater than the number of data bytes comprising said R-S blocks;
• a modulo [(B-1)N/2)+converter;
• and
• a combining circuit for combining the output of said multiplying means and the output of said modulo converter and applying said combined signal to the input of said modulo converter.