Back to results
US 5,572,198 AGranted
Method and apparatus for routing in reduced switch matrices to provide one hundred percent coverage
AssigneeIntel Corporation
InventorJay Sturges
Life of this patent
Estimating the term…
Abstract
A field programmable gate array in which the pattern of a first smaller switch matrix is continued into a number of other smaller reduced switch matrices necessary to provide full coverage for all of the input conductor combinations at the output conductors.
Claims30
A switch matrix comprising:
- a plurality of reduced switch matrices, each of the reduced switch matrices comprising:
- a plurality of rows of input conductors,
- a plurality of columns of output conductors logically intersecting the rows of input conductors, and
- a plurality of switching devices each arranged to connect one of the input conductors to one of the output conductors at an intersection, the plurality of switching devices forming a pattern of logical interconnections of input conductors and output conductors, the pattern being a fraction of a total of logical intersections;
- wherein the pattern of logical interconnections in a first one of the reduced switch matrices being continued in additional ones of the reduced switch matrices until complete coverage of all possible combinations of input conductors is obtained on the output conductors.
2 more elements
A programmable logic circuit comprising:
- a switch matrix comprising:
- a plurality of reduced switch matrices, each of the reduced switch matrices comprising:
- a plurality of rows of input conductors,
- a plurality of columns of output conductors logically intersecting the rows of input conductors, and
- a plurality of switching devices each arranged to connect one of the input conductors to one of the output conductors at an intersection, the plurality of switching devices forming a pattern of logical interconnections of input conductors and output conductors, the pattern being a fraction of a total of logical intersections;
- wherein the pattern of logical interconnections in first one of the reduced switch matrices being continued in additional ones of the reduced switch matrices until complete coverage of all possible combinations of input conductors is obtained on the output conductors;
- a plurality of AND gates connected to the output conductors;
- and
- a plurality of OR gates connected to receive output signals from the AND gates.
6 more elements
A digital system comprising:
- a processor;
- main memory;
- a bus associated with the processor and main memory;
- and
- a component joined to the bus including a switch matrix comprising:
- a plurality of reduced switch matrices, each of the reduced switch matrices comprising:
- a plurality of rows of input conductors,
- a plurality of columns of output conductors logically intersecting the rows of input conductors, and
- a plurality of switching devices each arranged to connect one of the input conductors to one of the output conductors at an intersection, the plurality of switching devices forming a pattern of logical interconnections of input conductors and output conductors, the pattern being a fraction of a total of logical intersections;
- wherein the pattern of logical interconnections in a first one of the reduced switch matrices being continued in additional ones of the reduced switch matrices until complete coverage of all possible combinations of input conductors is obtained on the output conductors.
7 more elements
Dependencies are inferred from the claim text.