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US 5,572,148 AGranted
Programmable logic array integrated circuit with general-purpose memory configurable as a random access or FIFO memory
AssigneeAltera Corporation
InventorsCraig S. Lytle, Donald F. Faria
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Abstract
A programmable logic device integrated circuit incorporating a memory block. The memory block (250) is a general-purpose memory configurable as a random access memory (RAM) or a first-in first-out (FIFO) memory. In one embodiment, the organization of memory block (250) may have variable word size and depth size. Memory block (250) is coupled to a programmable interconnect array (213). Signals from the programmable interconnect array (213) may be programmably coupled to the data, address, and control inputs of the memory block. Data output and status flag signals from the memory block are programmably coupled to the programmable interconnect array (213).
Claims36
A programmable logic device integrated circuit comprising:
- a first plurality of conductors, extending along a first dimension of a two-dimensional array;
- a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;
- a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;
- and
- a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode.
2 more elements
A programmable logic device integrated circuit comprising:
- a first plurality of conductors, extending along a first dimension of a two-dimensional array;
- a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;
- a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;
- a memory block, programmably coupled to said first plurality of conductors;
- and
- an address bus multiplexer, wherein said address bus multiplexer selectably couples an input pad or said first plurality of conductors to an address bus of said memory block.
3 more elements
A programmable logic device integrated circuit comprising:
- a first plurality of conductors, extending along a first dimension of a two-dimensional array;
- a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;
- a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;
- a memory block, programmably coupled to said first plurality of conductors;
- and
- a data bus multiplexer, wherein said data bus multiplexer selectably couples an input pad, said first plurality of conductors, or an output of said memory block to a data bus of said memory block.
3 more elements
A programmable logic device integrated circuit comprising:
- a first plurality of conductors, extending along a first dimension of a two-dimensional array;
- a second plurality of conductors, extending along a second dimension of said two-dimensional array, wherein said second plurality of conductors is programmably coupled to said first plurality of conductors;
- a plurality of logic array blocks, programmably coupled to said first plurality of conductors and second plurality of conductors;
- a memory block, programmably coupled to said first plurality of conductors, wherein said memory block is programmably configurable as a random access memory in a first mode and a first-in, first-out memory in a second mode, wherein said memory block further comprises a plurality of control inputs programmably coupled to said first plurality of conductors, wherein said plurality of control inputs control operations of said memory block, wherein said memory block generates a plurality of flag outputs programmably coupled to said first plurality of conductors, wherein said plurality of flag outputs indicate a status of said memory block;
- an address bus multiplexer, wherein said multiplexer selectably couples an input pad or said first plurality of conductors to an address bus of said memory block;
- and
- a data bus multiplexer, wherein said multiplexer selectably couples said input pad, said first plurality of conductors, or an output of said memory block to a data bus of said memory block.
4 more elements
A memory block for a programmable logic device comprising:
- at least one random access memory;
- a read pointer latch;
- a write pointer latch;
- a read address multiplexer, coupled to a read address input of said at least one random access memory, wherein said read address multiplexer programmably couples said read pointer latch to a read address input of said at least one random access memory;
- and
- a write address multiplexer, coupled to a write address input of said at least one random access memory, wherein said write address multiplexer programmably couples said write pointer latch to a write address input of said at least one random access memory.
3 more elements
A memory block for a programmable logic device comprising:
- a first random access memory;
- a second random address memory;
- a first output latch, coupled to said first random access memory;
- a second output latch, coupled to said second random access memory;
- and
- an output multiplexer, coupled to said first output latch and said second output latch, wherein said output multiplexer programmably couples said first output latch or said second output latch to an input-output pad, wherein selection of said output multiplexer is based on least significant bits of an address bus, wherein said address bus is coupled to said first random access memory, said second random access memory, and said output multiplexer.
3 more elements
Dependencies are inferred from the claim text.