US 5,570,307 A · Digital randomizer for on-chip generation and storage of random self-programming data block

Abstract

A purely digital randomizer system generates an undeterministic data block using standard cell library units and includes a random number generator. The generator preferably includes at least two metastable blocks that each include a plurality of D-type flip-flops. Each flip-flop is coupled to a dedicated free-running oscillator whose frequency is based on a relative prime number for each frequency leg. Each of the D-type flip-flops is also coupled to receive a common jitter clock signal. The flip-flops are thus forcibly operated in a metastable state by intentionally violating the flip-flop set-up or hold time margins of incoming data relative to the jitter clock. To further maximize entropy, the flip-flop outputs are exclusively `OR`d ("EX-OR'd") and then passed through first and second shift registers of uneven and preferably even and odd bit lengths. Preferably each shift register includes at least one metastably-operated D-type flip-flop, to further promote randomness. The shift register outputs are combined in an EX-OR tree are cross-fed back to the EX-ORs at the shift register inputs. The input from each shift register is then EX-OR'd and clocked out with a system clock to provide first and second channels of undeterministic data.

Claims29

Dependent claims

A system for generating an undeterministic data signal, comprising:

a plurality of N1 D-type flip-flops, each flip-flop including:
a clock input port coupled to a common jitter clock signal;
a delay input port coupled to receive a dedicated free-running oscillator signal;
and
an output port;
a jitter clock, outputting a phase noise signal causing said flip-flops to operate metastably;
N1 free-running oscillators, each oscillator oscillating at a frequency that is a prime number relative to a frequency of oscillation of each other of said oscillators, each oscillator having an output port coupled to a said delay input port of one of said flip-flops;
and
exclusive-OR means for outputting the undeterministic data signal, said exclusive-OR means coupled to receive an output signal from each said D-type flip-flop;
wherein N1 is an integer.

7 more elements

A system for generating first and second channels of undeterministic data signals, comprising:

a first plurality of N1 D-type flip-flops, each flip-flop including:
a clock input port coupled to a common jitter clock signal;
a delay input port coupled to receive a dedicated free-running oscillator signal;
and
an output port;
a second plurality of N2 D-type flip-flops, each flip-flop including:
a clock input port coupled to a common jitter clock signal;
a delay input port coupled to receive a dedicated free-running oscillator signal;
and
an output port;
a jitter clock, outputting a phase noise signal causing said flip-flops to operate metastably;
N1 free-running oscillators, each oscillator oscillating at a frequency that is a prime number relative to a frequency of oscillation of each other of said oscillators, each oscillator having an output port coupled to a said delay input of one of said flip-flops comprising said first plurality N1 of D-type flip-flops;
N2 free-running oscillators, each oscillator oscillating at a frequency that is a prime number relative to a frequency of oscillation of each other of said oscillators in said system, each oscillator having an output port coupled to a said delay input of one of said flip-flops comprising said second plurality of N2 D-type flip-flops;
first exclusive-OR means for outputting a first channel of undeterministic data, said first exclusive-OR means coupled to receive an output signal from each said D-type flip-flop in said first plurality of N1 D-type flip-flops;
second exclusive-OR means for outputting a second channel of undeterministic data, said second exclusive-OR means coupled to receive an output signal from each said D-type flip-flop in said second plurality of N2 D-type flip-flops;
an M-bit shift register having an input port coupled to an output port of said first exclusive-OR means, having a clock port coupled to receive said jitter clock signal, and having an output port;
an N-bit shift register having an input port coupled to an output port of said second exclusive-OR means, having a clock port coupled to receive said jitter clock signal, and having an output port;
wherein N1 and N2 are integers, and wherein first and second channels of undeterministic data signal are provided at said output port of said M-bit shift register and said N-bit shift register.

15 more elements

A method for generating an undeterministic data signal, the method including the following steps:

(a) providing a plurality of N1 D-type flip-flops, each flip-flop including:
a clock input port coupled to a common jitter clock signal, where N1 is an integer;
a delay input port coupled to receive a dedicated free-running oscillator signal;
and
an output port;
(b) providing a jitter clock, outputting a phase noise signal causing said flip-flops to operate metastably;
(c) providing N1 free-running oscillators, each oscillator oscillating at a frequency that is a prime number relative to a frequency of oscillation of each other of said oscillators, each oscillator having an output port coupled to a said delay input port of one of said flip-flops;
(d) providing exclusive-OR means for outputting the undeterministic data signal, wherein said exclusive-OR means is coupled to receive an output signal from each said D-type flip-flop.

5 more elements

A method for generating first and second channels of undeterministic data signals, the method including the following steps:

(a) providing a first plurality of N1 D-type flip-flops, each flip-flop including:
a clock input port coupled to a common jitter clock signal;
a delay input port coupled to receive a dedicated free running oscillator signal;
and
an output port;
(b) providing a second plurality of N2 D-type flip-flops, each flip-flop including:
a clock input port coupled to a common jitter clock signal;
a delay input port coupled to receive a dedicated free running oscillator signal;
and
an output port;
(c) providing a jitter clock, outputting a phase noise signal causing said flip-flops to operate metastably;
(d) providing N1 free-running oscillators, each oscillator oscillating at a frequency that is a prime number relative to a frequency of oscillation of each other of said oscillators, each oscillator having an output port coupled to a said delay input of one of said flip-flops comprising said first plurality of N1 D-type flip-flops;
(e) providing N2 free-running oscillators, each oscillator oscillating at a frequency that is a prime number relative to a frequency of oscillation of each other of said oscillators in said system, each oscillator having an output port coupled to a said delay input of one of said flip-flops comprising said second plurality of N2 D-type flip-flops;
(f) providing first exclusive-OR means for outputting a first channel of undeterministic data, wherein said first exclusive-OR means is coupled to receive an output signal from each said D-type flip-flop in said first plurality of N1 D-type flip-flops;
(g) providing second exclusive-OR means for outputting a second channel of undeterministic data, wherein said second exclusive-OR means is coupled to receive an output signal from each said D-type flip-flop in said second plurality of N2 D-type flip-flops;
(h) providing an M-bit shift register having an input port coupled to said output port of said first exclusive-OR means, having a clock port coupled to receive said jitter clock signal, and having an output port;
and
(i) providing an N-bit shift register having an input port coupled to said output port of said second exclusive-OR means, having a clock port coupled to receive said jitter clock signal, and having an output port;
wherein N1 and N2 are integers;
wherein M and N are numbers having a characteristic selected from the group consisting of (a) M and N are unequal, (b) M is even and N is odd, (c) the smaller of M and N exceeds 9, and (d) the difference between M and N exceeds 5;
wherein first and second channels of undeterministic data signal are present at said output port of said M-bit shift register and said N-bit shift register.

18 more elements

Dependencies are inferred from the claim text.

Digital randomizer for on-chip generation and storage of random self-programming data block

Life of this patent

Digital randomizer for on-chip generation and storage of random self-programming data block

Life of this patent

Abstract

Claims29