Semiconductor device employing crystallization catalyst

A semiconductor circuit comprising:

• a transistor comprising an active region made of a crystalline silicon film provided on a substrate;
• and
• another transistor comprising another active region made of an amorphous silicon film,
• wherein a concentration of a catalyst element in said crystalline silicon film is in the range of 10.sup.17 cm.sup.-3 to 10.sup.20 cm.sup.-3, and a concentration of a catalyst element in said amorphous silicon film is lower than 10.sup.17 cm.sup.-3.

A semiconductor circuit comprising:

• a transistor comprising an active region made of a crystalline silicon film;
• and
• another transistor comprising another active region made of an amorphous silicon film,
• wherein a concentration of a catalyst element in said crystalline silicon film is in the range of 1.times.10.sup.17 cm.sup.-3 to 1.times.10.sup.20 cm.sup.-3 and is higher than a concentration of a catalyst element in said amorphous silicon film.

A semiconductor circuit comprising:

• a transistor comprising an active region made of a crystalline silicon island provided on a substrate, said crystalline silicon island having a thickness of 1000 .ANG. or less;
• and
• another transistor comprising another active region made of an amorphous silicon film,
• wherein a concentration of a catalyst element in said crystalline silicon island is in the range of 10.sup.17 cm.sup.-3 to 10.sup.20 cm.sup.-3, and a concentration of a catalyst element in said amorphous silicon film is lower than 10.sup.17 cm.sup.-3.

A semiconductor circuit comprising:

• a transistor comprising an active region made of a crystalline silicon island provided on a substrate, said crystalline silicon island having a thickness of 1000.ANG. or less;
• and
• another transistor comprising another active region made of an amorphous silicon film,
• wherein a concentration of a catalyst element contained in said crystalline silicon island is in the range of 1.times.10.sup.17 cm.sup.-3 to 1.times.10.sup.20 cm.sup.-3 and is 10 times or more than that of a catalyst element contained in said amorphous silicon film.

A semiconductor circuit comprising:

• a transistor comprising an active region made of a crystalline silicon island having a thickness of 1000.ANG. or less;
• and
• another transistor comprising another active region made of an amorphous silicon film,
• wherein a concentration of a catalyst element in said crystalline silicon island is in the range of 1.times.10.sup.17 cm.sup.-3 to 1.times.10.sup.20 cm.sup.-3 and is higher than a concentration of a catalyst element in said amorphous silicon film.

An electro-optical device comprising:

• a substrate having a pixel region and a peripheral circuit region;
• a first plurality of thin film transistors formed over said pixel region of said substrate, each of said first plurality of thin film transistors comprising a gate electrode, a gate insulating layer formed on said gate electrode and a first semiconductor layer formed on said gate insulating layer;
• and
• a second plurality of thin film transistors formed over said peripheral circuit region of said substrate for driving said first plurality of thin film transistors, each of said second plurality of thin film transistors comprising a second semiconductor layer, a gate insulating film formed adjacent to said second semiconductor layer and a gate electrode adjacent to said second semiconductor layer,
• wherein each first semiconductor layer of the first plurality of thin film transistors has a lower crystallinity than each second semiconductor layer of the second plurality of thin film transistors, and wherein a concentration of a catalyst element in said second semiconductor layer is in the range of 10.sup.17 cm.sup.-3 to 10.sup.20 cm.sup.-3, and a concentration of a catalyst element in said each first semiconductor layer is lower than 10.sup.17 cm.sup.-3.

An electro-optical device comprising:

• a substrate having a pixel region and a peripheral circuit region;
• a first plurality of thin film transistors formed over said pixel region of said substrate, each of said first plurality of thin film transistors comprising a gate electrode, a gate insulating layer formed on said gate electrode and a first semiconductor layer formed on said gate insulating layer;
• and
• a second plurality of thin film transistors formed over said peripheral circuit region of said substrate for driving said first plurality of thin film transistors, each of said second plurality of thin film transistors comprising a second semiconductor layer, a gate insulating film adjacent to said second semiconductor layer and a gate electrode adjacent to said second semiconductor layer,
• wherein only each second semiconductor layer of the second plurality of thin film transistors is doped with a catalyst for promoting a crystallization thereof at a concentration in the range of 10.sup.17 cm.sup.-3 to 10.sup.20 cm.sup.-3 while each first semiconductor layer of the first plurality of thin film transistors is not doped with a catalyst for promoting a crystallization thereof and a concentration of a catalyst element in said first semiconductor layer is lower than 10.sup.17 cm .sup.-3.