Built-in self test for integrated circuits having read/write memory

An integrated circuit with read/write memory and read/write memory self testing capability comprising:

• read/write memory having a plurality of data storage locations, each location having a unique address;
• a controller responsive to a test enable signal and operative to generate and store test data at various locations in said read/write memory;
• a comparator responsive to said test data provided by said controller and to retrieved data read from said read/write memory, said comparator comparing said test data and said retrieved data for corresponding locations in said read/write memory and producing error signals indicating that said retrieved data does not corresponds correctly to said test data;
• and
• input/output circuitry including at least one register capable of storing an address of a read/write memory location where an error has been detected as indicated by said error signals, and capable of outputting said address of a read/write memory location to provide an indication of where said error occurred in said read/write memory, and wherein said input/output circuitry includes a failed test counter which counts the error signals produced by said comparator.

An integrated circuit comprising:

• random access memory (RAM) comprising a plurality of data storage locations each having a unique address;
• and
• a built-in self tester coupled to said RAM and to a plurality of input/output (I/O) ports of said integrated circuit, said tester including:
• (a) a RAM BIST controller for controlling said RAM during a test, said RAM including data, address, and control lines;
• (b) a comparator responsive to outputs of said RAM BIST controller and said RAM and operative to develop an error signal;
• and
• (c) BIST I/O responsive to outputs of said comparator and having at least one output coupled to at least one of said I/O ports, said BIST I/O including at least one register capable of storing at least one address of a data storage location in said RAM that malfunctioned during said test, said BIST I/O being further capable of outputting said at least one address via said at least one I/O port.

A method of testing memory on an integrated circuit comprising:

• activating at least one read/write memory location on said integrated circuit, said memory location having an address;
• and
• activating a built-in self tester on said integrated circuit to:
• (a) write test data to said memory location;
• (b) read said test data as retrieved data from said memory location;
• (c) compare said test data with said retrieved data and developing an error signal when said retrieved data does not correctly correspond to said test data;
• (d) store in an error address register said address of said memory location in response to said error signal;
• and
• (e) outputting contents Of said error address register in response to an output command received by said built in self tester.