MOS current source layout technique to minimize deviation

Abstract

A current source DAC is provided including a plurality of current source cells arranged in an array of a plurality of columns and rows. Among the plurality of current source cells is a plurality of least significant bit cells, wherein each least significant bit cell includes at least one current source cell. The plurality of least significant bit cells includes current source cells from among a centrally located column of the array. Also among the plurality of current source cells is a plurality of most significant bit cells. Each most significant bit cell includes a plurality of current source cells electrically added together and physically located along a diagonal path across the columns and rows of the array. The current source cell include CMOS transistors. The physical layout and electrical connection scheme reduces DNL errors due to transistor process gradients.

Dependencies are inferred from the claim text.