Method and workpiece for connecting a thin layer to a monolithic electronic module's surface and associated module packaging

A method for establishing a metallization layer on a side surface of an electronic module, said electronic module comprising a plurality of stacked integrated circuit chips having a plurality of edge surfaces that at least partially define the side surface of the electronic module, said method comprising the steps of:

• (a) forming a metallization layer on a first surface of a substrate, said substrate having said first surface, a second surface, and a plurality of electrically conductive vias extending between said first surface and said second surface, said substrate further including an active circuit layer disposed on said second surface and a plurality of electrical contacts for facilitating electrical contact to a circuit external to said electronic module, said metallization layer and said active circuit layer being electrically connected by said plurality of electrically conductive vias;
• (b) coupling said metallization layer to a temporary support via a temporary adhesive layer, wherein said steps (a) and (b) are performed physically independent from the electronic module;
• (c) electrically coupling the metallization layer to the side surface of the electronic module such that said metallization layer mechanically bonds to said side surface and said temporary support is coupled to said electronic module, wherein said metallization layer at least partially interconnects said plurality of stacked integrated circuit chips comprising said electronic module;
• and
• (d) detaching the temporary support from said electronic module along the temporary adhesive layer, wherein said metallization layer remains bonded to said side surface of the electronic module and said substrate and said active circuit layer having said plurality of electrical contacts remains coupled to said electronic module.

A method for forming an electronic package comprising the steps of:

• (a) providing an electronic module comprising a plurality of stacked integrated circuit chips and having a planar side surface;
• (b) providing an interposer comprising a first planar main surface and an active circuit layer;
• and
• (c) electrically coupling said planar side surface of said electronic module to said first planar main surface of said interposer such that said active circuit layer functions in conjunction with the electronic module.

A method for forming an electronic package comprising the steps of:

• (a) providing an electronic module comprising a plurality of stacked integrated circuit chips, said electronic module having a planar surface;
• (b) providing a cavity substrate having a cavity therein;
• (c) providing an active integrated circuit chip;
• and
• (d) mechanically coupling said active integrated circuit chip and said electronic module to said cavity substrate such that said electronic module and said active integrated circuit chip are recessed within said cavity and said active integrated circuit chip is disposed between said cavity substrate and said planar surface of said electronic module.

A method for forming an electronic package comprising the steps of:

• (a) providing an electronic module comprising a plurality of stacked integrated circuit chips, said electronic module having a planar surface;
• (b) providing a cavity substrate having both a cavity and an opening therein;
• and
• (c) mechanically coupling the planar surface of the electronic module to the cavity substrate, wherein said electronic module is recessed within said cavity.

A method for forming a computer unit comprising the steps of:

• (a) providing a processor chip having a planar main surface, said processor chip including a cache memory controller;
• (b) providing a first electronic module comprising a plurality of stacked integrated circuit (IC) chips and having a first planar surface, said first electronic module including a cache memory circuit;
• and
• (c) mechanically and electrically coupling the first planar surface of the first electronic module to the planar surface of the processor chip such that the cache memory controller is electrically connected to the cache memory circuit.