Method and apparatus for a finite impulse response filter processor
AssigneesSigmatel, Inc., Dallas Semiconductor Corporation
InventorGregg S. Kodra
Life of this patent
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Abstract
A method and apparatus for performing finite impulse response filtering in real time is accomplished by taking advantage of symmetrical FIR coefficients of FIR filters in audio equipment. Due to the symmetry of the coefficients, each coefficient, other than the T0 coefficient, has an almost identical counterpart. Thus, only one of the identical coefficient needs to be stored and is used in conjunction with two data points. The two data points are summed together prior to multiplication by the corresponding coefficient to produce an accumulated resultant. This process repeats for each pair of data points, and corresponding FIR coefficient, until a final resultant is obtained.
Claims16
A finite impulse response filter (FIR) processor having a plurality of FIR coefficients symmetrical about a center FIR coefficient such that each of said FIR coefficients has a corresponding identical FIR coefficient counterpart, said FIR processor comprising:
- memory having a first memory unit for storing only one of each set of identical FIR coefficients and a second memory unit for temporarily storing a plurality of data points representing digitized analog signals corresponding to said FIR coefficients;
- program control logic operably coupled to the memory for providing, at a clock rate, addresses to the memory for retrieval of one FIR coefficient and a first data point corresponding to the FIR coefficient and a second data point corresponding to the identical counterpart of the FIR coefficient;
- adder operably coupled to the first memory unit for adding the first data point and the second data point together to produce a resultant;
- and
- a multiply-accumulator for multiplying the resultant and the FIR coefficient to produce an accumulated resultant wherein said multiply-accumulator is operably coupled to the adder and the second memory unit such that the FIR coefficient bypasses the adder upon transfer from the second memory unit to the multiply-accumulator and such that the resultant transfers from the adder to the multiply-accumulator.
A method for performing finite impulse response (FIR) filtering on a digitized analog signal, by utilizing a plurality of FIR coefficients which are symmetrical about a center FIR coefficient such that each of the FIR coefficients has a corresponding identical FIR coefficient counterpart, the method comprising the steps of:
- a) storing only one of each set of identical FIR coefficients in a first memory unit;
- b) storing a plurality of data points representing the digitized analog signal in a second memory unit;
- c) retrieving from the first memory unit one FIR coefficient;
- d) retrieving from the second memory unit a first data point corresponding to the FIR coefficient;
- e) retrieving from the second memory unit a second data point corresponding to the identical counterpart of the FIR coefficient;
- f) adding the first data point and the second data point to produce a resultant;
- g) multiplying the FIR coefficient and the resultant to produce an intermediate resultant;
- and
- h) accumulating the intermediate resultant with other intermediate resultants until a final resultant is obtained, wherein the final resultant represents an FIR filtered representation of the digitized analog signal.
A sound system coder/decoder (CODEC) comprising:
- analog-to-digital converter;
- digital-to-analog converter;
- a low pass decimation filter operably coupled to the analog-to-digital converter, wherein the low pass decimation filter decimates digital signals received from the analog-to-digital converter;
- an interpolation filter operably coupled to the digital-to-analog converter, wherein the interpolation filter interpolates a processed digital signal;
- and
- a finite impulse response filter (FIR) processor having a plurality of FIR coefficients symmetrical about a center FIR coefficient such that each of said FIR coefficients has a corresponding identical FIR coefficient counterpart operably coupled to supply the processed digital signal to the interpolation filter, wherein the FIR processor includes:
- memory having a first memory unit for storing only one of each set identical FIR coefficients and a second memory unit for temporarily storing a plurality of data points representing digitized analog signals received via the low pass decimation filter;
- program control logic operably coupled to the memory for providing, at a clock rate, addresses to the memory for retrieval of one FIR coefficient and a first data point corresponding to the FIR coefficient and a second data point corresponding to the identical counterpart of the FIR coefficient that represent at least a portion of the digitized analog signals;
- adder operably coupled to the first memory unit for adding the first data point and the second data point together to produce a resultant;
- and
- a multiply-accumulator for multiplying the resultant and the FIR coefficient to produce an accumulated resultant wherein said multiply-accumulator is operably coupled to the adder in the second memory unit such that the FIR coefficient bypasses the adder upon transfer from the second memory unit to the multiply-accumulator and such that the resultant transfers from the adder to the multiply-accumulator.
Dependencies are inferred from the claim text.