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US 5,563,839 AGranted
Semiconductor memory device having a sleep mode
AssigneeSimtek
InventorsChristian E. Herdt, Albert S. Weiner
Life of this patent
Estimating the term…
Abstract
The present invention provides a computer memory device having a sleep mode characterized by extremely low current consumption and relatively large turn on delay. The invention includes circuitry for disabling current sinking elements internal to said device in response to a sleep signal. In one embodiment, the invention includes circuitry for disconnecting the bit lines and memory cell loads of a nonvolatile static random access memory (nvSRAM) array from a source of power in response to a sleep signal. This embodiment is capable of first transferring the data stored in a volatile portion of the array to a nonvolatile portion of the array before entering sleep mode to prevent loss of the data.
Claims30
A nonvolatile static random access memory (nvSRAM) device having a sleep mode, comprising:
- a nonvolatile static random access memory cell, having:
- a static random access memory (SRAM) portion which will lose any data located therein if power is removed;
- and
- a nonvolatile portion which will retain any data located therein if power is removed;
- wherein said nonvolatile portion is operatively connected to said SRAM portion for transferring a bit of data from said SRAM portion to said nonvolatile portion in response to a store signal and for transferring a bit of data from said nonvolatile portion to said SRAM portion in response to a recall signal;
- means for monitoring power being provided to the device and for generating a store signal upon detecting a loss of power and a recall signal upon detecting a restoration of power, wherein said means for monitoring power includes circuitry that consumes power;
- and
- means, in response to a sleep signal, for disabling at least a portion of said circuitry in said means for monitoring power to reduce power consumption.
5 more elements
A nonvolatile static random access memory device having a sleep mode, comprising:
- a nonvolatile static random access memory cell, having:
- a static random access memory (SRAM) portion that is capable of receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data back to said exterior environment, wherein a bit of data will not be retained if power is removed;
- and
- a nonvolatile portion operatively connected to said SRAM portion for transferring a bit of data from said SRAM portion to said nonvolatile portion in response to a store signal and transferring a bit of data from said nonvolatile portion to said SRAM portion in response to a recall signal, wherein a bit of data retained in said nonvolatile portion will be retained if power is removed;
- means for facilitating at least one of receiving, transmitting, storing and recalling data, said means for facilitating consuming power and having a relatively high time constant;
- and
- means, in response to a sleep signal, for disabling said means for facilitating to reduce power consumption.
4 more elements
A nonvolatile static random access memory device having a sleep mode, comprising:
- a nonvolatile static random access memory (nvSRAM) cell having:
- a static random access memory (SRAM) portion for receiving a bit of data from an exterior environment, retaining said bit of data, and transmitting said bit of data back to said exterior environment, wherein a retained bit of data will be lost if power is removed;
- and
- a nonvolatile portion operatively connected to said SRAM portion for transferring a bit of data from said SRAM portion to said nonvolatile portion in response to a store signal and for transferring a bit of data from said nonvolatile portion to said SRAM portion in response to a recall signal, wherein a bit of data retained in said nonvolatile portion will not be lost if power is removed;
- input buffer means for receiving data from said exterior environment and for sending said data to circuitry internal to said nvSRAM device, wherein said input buffer means consumes power;
- and
- means, in response to a sleep signal, for disabling said input buffer means to reduce power consumption.
4 more elements
A semiconductor memory device having a sleep mode, comprising:
- a memory capable of retaining a bit of data and transmitting said bit of data to an exterior environment, wherein said memory consumes power during a standby mode;
- wherein said memory includes at least one bit line which consumes power through undesirable junction leakage whenever the voltage on said bit line is substantially different from the voltage on an underlying substrate;
- and
- means for reducing, relative to said standby mode, the power consumed by said memory in response to a sleep signal;
- wherein said means for reducing power consumption includes means for holding said bit line at substantially the same voltage as said underlying substrate in response to said sleep signal.
2 more elements
A semiconductor memory device having a sleep mode, comprising:
- a memory capable of retaining a bit of data and transmitting said bit of data to an exterior environment, wherein said memory consumes power during a standby mode;
- wherein said memory includes at least one bit line which consumes power through undesirable junction leakage whenever the voltage on said bit line is substantially different from the voltage on an underlying substrate;
- and
- means for reducing, relative to said standby mode, the power consumed by said memory in response to a sleep signal;
- wherein said means for reducing power consumption includes means for disconnecting said bit line from a source of power in response to said sleep signal.
2 more elements
A semiconductor memory device having a sleep mode, comprising:
- a memory capable of retaining a bit of data and transmitting said bit of data to an exterior environment, wherein said memory consumes power during a standby mode;
- wherein said memory includes at least one memory load which consumes power whenever a voltage drop exists across it;
- and
- means for reducing, relative to said standby mode, the power consumed by said memory in response to a sleep signal;
- wherein said means for reducing power consumption includes means for holding said memory load at substantially the same voltage as said underlying substrate in response to said sleep signal.
2 more elements
A semiconductor memory device having a sleep mode, comprising:
- a memory capable of retaining a bit of data and transmitting said bit of data to an exterior environment, wherein said memory consumes power during a standby mode;
- wherein said memory includes at least one memory load which consumes power whenever a voltage drop exists across it;
- and
- means for reducing, relative to said standby mode, the power consumed by said memory in response to a sleep signal;
- wherein said means for reducing power consumption includes means for disconnecting said memory load from a source of power in response to said sleep signal.
2 more elements
A semiconductor memory device having a sleep mode, comprising:
- a memory capable of retaining a bit of data and transmitting said bit of data to an exterior environment, wherein said memory consumes power during a standby mode;
- wherein said memory includes at least one input buffer which consumes power whenever an input voltage at an intermediate level between power supply and ground is applied to said at least one input buffer;
- and
- means for reducing, relative to said standby mode, the power consumed by said memory in response to a sleep signal;
- wherein said means for reducing power consumption includes means for disabling said input buffer in response to said sleep signal.
2 more elements
A nonvolatile static random access memory (nvSRAM) device having a sleep mode, comprising:
- a nonvolatile static random access memory cell, having:
- a static random access memory (SRAM) portion which will lose any data located therein if power is removed;
- and
- a nonvolatile portion which will retain any data located therein if power is removed;
- wherein said nonvolatile portion is operatively connected to said SRAM portion for transferring a bit of data from said SRAM portion to said nonvolatile portion in response to a store signal and for transferring a bit of data from said nonvolatile portion to said SRAM portion in response to a recall signal;
- means for determining whether there has been a loss of power and generating said store signal when there has been a loss of power, wherein said means for determining whether there has been a loss of power consumes power;
- means for isolating the device from an external power supply if there is a loss of system power, wherein said means for isolating consumes power;
- means for determining whether power is adequate for operation of said SRAM portion after there has been an absence of power and for generating a recall signal, wherein said means for determining whether power is adequate consumes power;
- a memory load operatively connected to said nonvolatile static random access memory cell, wherein said memory load consumes power;
- a bit line operatively connected to said nonvolatile static random access memory cell and that provides a pathway for transmitting and receiving data between said SRAM portion and the exterior environment, wherein said bit line consumes power;
- input buffer means for receiving data from an exterior environment and for sending said data to circuitry internal to said nvSRAM device, wherein said input buffer means consumes power;
- and
- means, in response to a sleep signal, for deactivating said means for determining whether there has been a loss of power, said means for isolating, said means for determining whether power is adequate, said memory load, said bit line and said input buffer means to reduce power consumption.
10 more elements
Dependencies are inferred from the claim text.