Fast high precision discrete-time analog finite impulse response filter

A discrete time analog finite impulse response filter comprising:

• (a) a plurality of analog storage devices for storing a corresponding plurality of analog sample values from a continuous time analog signal;
• (b) a plurality of digital storage devices for storing a corresponding plurality of digital weight values;
• and
• (c) a plurality of analog multiplying circuits for multiplying the analog sample values by the digital weight values, wherein the precision of each of the analog multiplying circuits increases as a corresponding setup time increases;
• wherein a predetermined number of the digital weight values are set to zero in order to increase the setup time, and thereby the precision, of the analog multiplying circuits.

A discrete time analog finite impulse response filter comprising:

• (a) a plurality of analog storage devices for storing a corresponding plurality of analog sample values from a continuous time analog signal;
• (b) a plurality of digital storage devices for storing a corresponding plurality of digital weight values;
• (c) a plurality of analog multiplying circuits for multiplying the analog sample values by the digital weight values, wherein each of the analog multiplying circuits comprises a plurality of current source circuits each producing a respective output current proportional to P.sup.j *x(Ai) where j is an integer representing a bit in one of the digital weight values, P is the base of the digital weight values, and x(Ai) is one of the analog sample values;
• and
• (d) an input signal for receiving a periodic clock signal for clocking the operation of the filter;
• wherein:
• (a) each of the analog sample values is stored in one of the analog storage devices for a predetermined number of clock periods and then replaced by a subsequent one of the analog sample values;
• and
• (b) each of the digital weight values is shifted to a different one of the digital storage devices at each clock period.

A finite impulse response filter connectable to receive a discrete-time succession of analog sample values x(n) representing an analog input signal comprising:

• N number of analog sample storage means for storing the sample analog values x(n);
• N number of analog multiplier circuits, each one of said multiplier circuits having a first operand input terminal connected to an associated one of said sample storage means, and having a second operand input terminal, and having an analog result signal output terminal;
• a weight storage means for storing N number of weight values W(k) where 0.ltoreq.k<N, said weight values W(k) applied to the second operand inputs of said multiplier circuits;
• an analog summing circuit connected to receive the analog result output signal of each said multiplier circuit, having a summed analog output signal y(n);
• and
• sequencing means connected to each of said analog sample storage means for distributing said succession of analog sample values x(n) to said analog sample storage means in a repeated sequence wherein the analog sample value x(n) is stored in one of the N analog storage means for N sample time periods, and after N sample time periods the analog sample value x(n) is replaced by the analog sample value x(n+N), said sequencing means also connected to said weight storage means for sequentially distributing said weight values W(k) to said multiplier circuits, wherein the distributing of the analog sample values x(n) is synchronized with the distributing of the weight values W(k) such that the summed analog output signal y(n) is characterized by:
• ##EQU5##

A signal processor comprising:

• sampling means for receiving and periodically sampling an analog signal input, over a succession of time periods, thereby producing a train of discrete-time analog samples x(n);
• analog sample storage means comprising N analog storage elements for holding N discrete analog samples from the train of discrete analog samples x(n);
• sequencing means connected to said sampling means for distributing the discrete analog samples x(n) to said analog storage elements in a repeated sequence, wherein the analog sample value x(n) is stored in one of the N analog storage elements for N sample time periods, and after N sample time periods the analog sample value x(n) is replaced by the analog sample value x(n+N);
• digital weight storage means for holding N digital words, hereinafter called N digital weights W(k), where 0.ltoreq.k<N, said digital weight storage means comprising N cells for holding the N digital weights W(k);
• multiplying means comprising N individual multiplying circuits for multiplying each of the N discrete analog samples stored in said analog storage means by one of the N digital weights W(k), said digital weight storage means supplying one of the N digital weights to each of the individual multiplying circuits;
• summing means for adding the products of said N individual multiplying circuits to produce an output signal y(n);
• and
• said sequencing means connected to said digital weight storage means for distributing the N digital weights W(k) in said digital weight storage means to the individual multiplying circuits in a repeated sequence wherein the distributing of the discrete analog sample values x(n) to the analog sample storage elements is synchronized with the distributing of the digital values W(k) to the individual multiplying circuits such that the summed analog output signal y(n) is characterized by:
• ##EQU6##

A finite impulse response filter connectable to receive a discrete-time succession of analog sample values x(n) representing an analog input signal comprising:

• N number of analog sample storage elements storing the sample analog values x(n);
• N number of analog multiplier circuits, each one of said multiplier circuits having a first operand input terminal connected to an associated one of said sample storage means, and having a second operand input terminal, and having an analog result signal output terminal;
• weight storage elements storing N number of weight values W(k) where 0.ltoreq.k<N, said weight values W(k) applied to the second operand inputs of said multiplier circuits;
• an analog summing circuit connected to receive the analog result output signal of each said multiplier circuit, having a summed analog output signal y(n);
• and
• a sequencer connected to each of said analog sample storage means for distributing said succession of analog sample values x(n) to said analog sample storage elements in a repeated sequence wherein the analog sample value x(n) is stored in one of the N analog storage elements for N sample time periods, and after N sample time periods the analog sample value x(n) is replaced by the analog sample value x(n+N), said sequencer also connected to said weight storage elements sequentially distributing said weight values W(k) to said multiplier circuits, wherein the distributing of the analog sample values x(n) is synchronized with the distributing of the weight values W(k) such that the summed analog output signal y(n) is characterized by:
• ##EQU7##

A signal processor comprising:

• sampling elements receiving and periodically sampling an analog signal input, over a succession of time periods, thereby producing a train of discrete-time analog samples x(n);
• N analog storage elements holding N discrete analog samples from the train of discrete analog samples x(n);
• a sequencer connected to said sampling elements distributing the discrete analog samples x(n) to said analog storage elements in a repeated sequence, wherein the analog sample value x(n) is stored in one of the N analog storage elements for N sample time periods, and after N sample time periods the analog sample value x(n) is replaced by the analog sample value x(n+N);
• digital weight storage elements holding N digital words, hereinafter called N digital weights W(k), where 0.ltoreq.k<N, said digital weight storage elements comprising N cells for holding the N digital weights W(k);
• N individual multiplying circuits multiplying each of the N discrete analog samples stored in said analog storage elements by one of the N digital weights W(k), said digital weight storage elements supplying one of the N digital weights to each of the individual multiplying circuits;
• a summing circuit adding the products of said N individual multiplying circuits to produce an output signal y(n);
• and
• said sequencer connected to said digital weight storage elements distributing the N digital weights W(k) in said digital weight storage elements to the individual multiplying circuits in a repeated sequence wherein the distributing of the discrete analog sample values x(n) to the analog sample storage elements is synchronized with the distributing of the digital values W(k) to the individual multiplying circuits such that the summed analog output signal y(n) is characterized by:
• ##EQU8##

A method for processing analog electrical signals comprising the steps of:

• receiving an analog signal input;
• periodically sampling said analog signal input over a succession of sample time periods thereby producing a train of discrete-time analog samples x(n);
• receiving and storing, in N number of analog memory elements, N discrete-time samples from said train of-discrete-time analog samples x(n);
• replacing each of the N stored discrete-time analog sample values in a repeated sequence with analog sample values from said train of discrete-time analog samples x(n) once every N sample time periods, wherein the analog sample value x(n) is stored for N sample time periods, and after N sample time periods the analog sample value x(n) is replaced by the analog sample value x(n+N);
• storing, in a weight storage memory, N values hereinafter called weights W(k) where 0.ltoreq.k<N;
• forming N analog products, using N analog multiplier circuits, by multiplying each of the N stored discrete-time analog sample values by one of the N weights W(k), wherein a different one of the N weights is sequentially accessible by each one of said multiplier circuits on each sample time period;
• producing a train of discrete-time analog output signals y(n) by summing said N analog products once each sample period using an analog summing circuit;
• and
• synchronizing and sequencing the sampling of the analog signal input x(t), the replacing of the stored discrete-time analog samples x(n), the sequential accessing of the digital weights W(k), and the forming and summing of N analog products such that the discrete-time analog output signal y(n) is characterized by:
• ##EQU9##