Active matrix panel and manufacturing method including TFTs having variable impurity concentration levels

An active matrix panel in which data signals are supplied to liquid crystal cells through a plurality of thin film transistors arranged in a matrix of pixels, comprising:

• an insulated substrate defining separate drive circuit and pixel areas on a surface thereon;
• a CMOS drive circuit formed within the drive circuit area of said insulated substrate, comprising:
• a first thin-film transistor of a first conductivity type including a first source-drain area having an impurity concentration of at least 1.times.10.sup.19 /cm.sup.3 ;
• and
• a second thin-film transistor of a second conductivity type having a second source-drain area;
• and
• a plurality of pixel thin-film transistors formed within the pixel area of said insulated substrate defining said matrix of pixels, wherein at least one of said pixel thin-film transistors comprises a third thin-film transistor of the first conductivity type, said third thin-film transistor including a third source-drain area having an area of impurity concentration less than said first source-drain area.

An active matrix panel in which data signals are supplied to liquid crystal cells through a plurality of thin film transistors arranged in matrix of pixels, comprising:

• an insulated substrate defining separate drive circuit and pixel areas on a surface thereon;
• a CMOS drive circuit formed within the drive circuit area of said insulated substrate, comprising:
• a first thin-film transistor of a first conductivity type including a first source drain area;
• and
• a second thin-film transistor of a second conductivity type having a second source-drain area;
• and
• a plurality of pixel thin-film transistors formed within the pixel area of said insulated substrate defining said matrix of pixels, wherein at least one of said pixel thin film transistors comprises a third thin-film transistor of the first conductivity type, said third thin-film transistor comprising:
• a third source-drain area including a high concentration contact area having an impurity concentration of at least 1.times.10.sup.19 /cm.sup.3 ;
• and
• a source-drain electrode electrically connected to said high concentration contact area.

An active matrix panel in which data signals are supplied to liquid crystal cells through a plurality of thin film transistors arranged in a pixel matrix, comprising:

• an insulated substrate defining separate drive circuit and pixel areas on a surface thereon;
• a CMOS drive circuit formed within the drive circuit area of said insulated substrate, comprising:
• a first thin-film transistor of a first conductivity type including a first source-drain area;
• and
• a second thin-film transistor of a second conductivity type having a second source-drain area;
• and
• a plurality of pixel thin-film transistors formed within the pixel area of said insulated substrate defining said matrix of pixels, wherein at least one of said pixel thin film transistors comprises a third thin-film transistor of the first conductivity type, said third thin-film transistor including a third source-drain area and a non-overlapping gate electrode offset laterally thereto.

A method for manufacturing an active matrix panel, comprising the steps of:

• (A) patterning first and second silicon films on a surface of an insulated substrate to form first and second thin-film transistors comprising a display drive circuit;
• (B) patterning a third silicon film on the surface of the insulated substrate to form a third thin-film transistor within a pixel matrix;
• (C) forming gate insulating films on the top surfaces of the first, second and third silicon films;
• (D) forming gate electrodes on portions of the gate insulating films;
• (E) implanting the first, second, and third silicon films with impurities of a first conductivity type at a dose less than 1.times.10.sup.14 /cm.sup.2 to create lightly-doped source-drain areas of a first conductivity type within the first, second, and third transistors;
• (F) masking the first and third silicon films with a first doping-resistant mask;
• (G) implanting the second silicon film with impurities of a second conductivity type at a dose of at least 1.times.10.sup.14 /cm.sup.2 to form source-drain areas of the second conductivity type within the second transistor;
• (H) removing the first doping-resistant mask;
• (I) masking the second silicon film, a gate electrode and a gate electrode periphery of the third silicon film with a second doping-resistant mask thereby leaving at least one portion of the third silicon film unmasked;
• and
• (J) implanting the first silicon film and the unmasked portion of the third silicon film with impurities of the first conductivity type at a dose of at least 1.times.10.sup.14 /cm.sup.2.

An active matrix panel in which data signals are supplied to liquid crystal cells through a plurality of thin film transistors arranged in a matrix of pixels, comprising:

• an insulated substrate defining separate drive circuit and pixel areas on a surface thereon;
• a CMOS drive circuit formed within the drive circuit area of said insulated substrate, comprising:
• a first thin-film transistor of a first conductivity type including a first source-drain area having an impurity concentration of at least 1.times.10.sup.19 cm.sup.3 ;
• and
• a second thin-film transistor of a second conductivity type having a second source-drain area;
• and
• a plurality of pixel thin-film transistors formed within the pixel area of said insulated substrate defining said matrix of pixels, wherein at least one of said pixel thin-film transistors comprises a third thin-film transistor of the first conductivity type, said third thin-film transistor comprising:
• a channel area;
• and
• source and drain regions interposing said channel area, each said source and drain region including a lightly-doped concentration area adjacent said channel area and a highly-doped concentration area adjacent said lightly-doped concentration area.

A method for manufacturing an active matrix panel, comprising the steps of:

• (A) patterning first and second silicon films on a surface of an insulated substrate to form first and second thin-film transistors comprising a display drive circuit;
• (B) patterning a third silicon film on the surface of the insulated substrate to form a third thin-film transistor within a pixel matrix;
• forming gate insulating films on the top surfaces of the first, second and third silicon films;
• (D) forming gate electrodes on portions of the gate insulating films;
• (E) implanting the first, second, and third silicon films with impurities of a first conductivity type to create lightly-doped source-drain areas of a first conductivity type within the first, second, and third transistors;
• (F) masking the first and third silicon films with a first doping-resistant mask;
• (G) implanting the second silicon film with impurities of a second conductivity type to form highly-doped source-drain areas of the second conductivity type within the second transistor;
• (H) removing the first doping-resistant mask;
• (I) masking the second silicon film, a gate electrode and a gate electrode periphery of the third silicon film with a second doping-resistant mask to leave at least one portion of the third silicon film unmasked;
• and
• (J) implanting the first silicon film and the unmasked portion of the third silicon film with impurities of the first conductivity type to develop highly-doped source-drain areas of the first conductivity type within the first transistor.

A method for manufacturing an active matrix panel, comprising the steps of:

• (A) patterning first and second silicon films on a surface of an insulated substrate to form first and second thin-film transistors comprising a display drive circuit;
• (B) patterning a third silicon film on the surface of the insulated substrate to form a third thin-film transistor within a pixel matrix;
• (C) forming gate insulating films on the top surfaces of the first, second and third silicon films;
• (D) forming gate electrodes on portions of the gate insulating films;
• (E) implanting the first, second, and third silicon films with impurities of a first conductivity type at a dose less than 1.times.10.sup.14 /cm.sup.2 ;
• (F) masking the first and third silicon films with a first doping-resistant mask;
• (G) implanting the second silicon film with impurities of a second conductivity type at a dose of at least 1.times.10.sup.14 /cm.sup.2 ;
• (H) removing the first doping-resistant mask;
• (I) masking the second silicon film, a gate electrode and a gate electrode periphery of the third silicon film with a second doping-resistant mask to leave at least one portion of the third silicon film unmasked;
• and
• (J) implanting the first silicon film and the unmasked portion of the third silicon film with impurities of the first conductivity type at a dose of at least 1.times.10.sup.14 /cm.sup.2.