Data processor for executing a fuzzy logic operation and method therefor

A data processor, comprising:

• a first address decoder for receiving a first input signal and decoding the first input signal to provide a first decoded signal when the first input signal is in a first membership function;
• a first memory having a first plurality of memory locations, the first memory being coupled to the first address decoder for receiving the first decoded signal, the first memory providing a first fuzzy input value in unary form from a first one of the first plurality of memory locations indicated by the first decoded signal;
• first logic means for selectively performing a first logic function using the first fuzzy input value, the first logic means being coupled to the first memory for receiving the first fuzzy input value and the first logic means providing a first minimum value;
• and
• second logic means for selectively performing a second logic function using the first minimum value, the second logic means being coupled to the first logic means for receiving the first minimum value and the second logic means providing a first output value.

A method for performing a fuzzy logic operation, comprising the steps of:

• receiving a first input signal;
• decoding the first input signal to access a first plurality of memory locations in a first membership function memory when the first input signal is included in the first membership function memory, the first plurality of memory locations corresponding to a first membership function;
• retrieving a first fuzzy input value in unary form from a first one of the first plurality of memory locations, the first fuzzy input value indicating a degree of membership of the first input signal in the first membership function;
• concurrently decoding the first input signal to access a second plurality of memory locations in the first membership function memory, the second plurality of memory locations corresponding to a second membership function;
• retrieving a second fuzzy input value in unary form from a first one of the second plurality of memory locations, the second fuzzy input value indicating a degree of membership of the second input signal in the second membership function;
• performing a first logic function selectively using the first fuzzy input value and a second fuzzy input value to provide a first minimum value;
• and
• performing a second logic function selectively using the first minimum value and the second fuzzy input value to provide a first output value.