Memories with burst mode access

A memory comprising:

• a set of consecutively addressed memory locations L1, . . . Ln;
• a plurality of sense amplifier circuits for amplifying contents of said memory locations;
• and
• an output for providing output signals from said plurality of sense amplifier circuits,
• wherein said memory has a burst mode operation for receiving an address and reading out to said output, in response to said address, any given number of memory locations in the sequence of consecutive addresses with wrap around so that the next location, if any, to be read out after said location Ln is said location L1, such that during said operation while the contents of any location L to be read out other than the last location to be read out are being transferred from said plurality of sense amplifier circuits to said output, the contents of another location to be read out after said location L are being provided to said plurality of sense amplifier circuits for amplification and subsequent transfer to said output, and
• wherein said memory further comprises a control circuit for selectively enabling said sense amplifier circuits so that said control circuit enables a sense amplifier circuit whose output signals are being transferred to the output of said memory but said control circuit does not enable all said sense amplifier circuits at the same time.

In a memory having a plurality of rows of memory locations and having a plurality of row decoders and one X-register for each said row decoder, a method of reading in a burst mode operation a plurality of consecutively addressed memory locations spanning more than one row, said method comprising the steps of:

• providing to said X-registers a row address of a first location to be read in said burst mode operation;
• for each row containing a location to be read in said burst mode operation, performing the steps of:
• providing by at least one of the X-registers to at least one of the row decoders signals identifying said row;
• activating by one of said row decoders at least a portion of said row;
• sensing and amplifying contents of at least one location of said row;
• and
• transferring amplified contents of at least one location of said row to an output of said memory;
• wherein for at least two locations L1 and L2 of said plurality which are in different rows having different row addresses in said memory, the step of sensing and amplifying the contents of said location L2 overlaps in time with the step of transferring the amplified contents of said location L1 to said output of said memory.

In a memory comprising a set of consecutively addressed memory locations L1, . . . , Ln, and a plurality of sense amplifier circuits, a method of reading out in burst mode a sequence of locations addressed consecutively with wrap around so that the next location to be read out after location Ln is location L1, said method comprising the steps of:

• receiving an address of a first location to be read out in burst mode;
• and
• in response to said address, for each location of said sequence performing the steps:
• sensing and amplifying contents of said location;
• and
• transferring amplified contents of said location to an output of said memory,
• wherein for any location L of said sequence other than the last location to be read out in said sequence, the transferring step for the location L overlaps in time with the sensing and amplifying step for another location to be read out after said location L in said sequence;
• and for at least one location LL of said sequence, before the sensing and amplifying step for said location LL, the sense amplifier circuit which is to perform the sensing and amplifying step for the location LL is enabled, and after the transferring step for location LL, the sense amplifier circuit that has performed the sensing and amplifying step for location LL is disabled, and another sense amplifier circuit which is to perform the sensing and amplifying step for another location to be read out in said sequence is enabled.

An integrated memory comprising:

• an array of memory locations, the array comprising a plurality of subarrays, each subarray comprising a predetermined number of groups of columns of the memory locations such that for any given column position in a group, the memory locations in any given row in the columns at said given position in the groups of the subarray have consecutive addresses;
• one X-decoder for each subarray;
• one X-register for each X-decoder;
• one Y-decoder for each subarray;
• one Y-register for each Y-decoder;
• one Y-select circuit for each subarray, the Y-select circuit being responsive to the Y-decoder of the subarray to select all the columns that occupy a selected position in the groups of the subarray;
• a plurality of sense amplifier circuits for each subarray, each sense amplifier circuit for amplifying signals from a column selected by the Y-select circuit of the subarray;
• a memory output;
• and
• a control circuit for selecting one of the sense amplifier circuits to provide data to the memory output,
• wherein in a burst mode read operation, at least one X-register provides to its respective X-decoder signals identifying a row in one of the subarrays, and at least one Y-register provides to its respective Y-decoder signals identifying a position of columns in the groups of one of the subarrays.