Interleaved cache for multiple accesses per clock cycle in a microprocessor

An interleaved cache memory for use in a microprocessor, wherein the microprocessor includes a plurality of execution units for executing a plurality of instructions per clock cycle, wherein a plurality of simultaneous data accesses to said cache memory are required for the execution of said plurality of instructions according to an access type, each of said plurality of data accesses being independently addressable, said cache memory comprising:

• a single-ported interleaved storage array comprising a plurality of banks of single-ported memory cells for storing a plurality of cache lines, each of said cells being independently addressable, wherein a portion of each of the plurality of cache lines is stored in each of the plurality of banks;
• access control logic coupled to the storage array, wherein the access control logic determines whether data stored in the locations requested by the plurality of accesses are contained in the storage array using tag matching;
• a plurality of decoding means for decoding the address of each of said plurality of data accesses to produce a plurality of decoded addresses;
• a plurality of bank selection means coupled to said plurality of decoding means and the storage array, wherein one of said plurality of banks is coupled with one of said plurality of bank selection means, said bank selection means for driving the plurality of decoded addresses onto the plurality of banks of said cells in parallel when the access control logic determines that data stored in the locations requested by the plurality of accesses is contained in the storage array using tag matching;
• and
• direction means coupled to said storage array for accommodating the plurality of data accesses, wherein the direction means directs data stored in locations requested by the plurality of data accesses from said storage array to the plurality of execution units, such that data is transferred between said storage array and said plurality of execution units multiple times per clock cycle.

An interleaved cache memory for use in a microprocessor, wherein the microprocessor includes a plurality of execution units for executing a plurality of instructions per clock cycle, wherein a plurality of simultaneous accesses to said cache memory are made during the execution of said plurality of instructions according to an access type, each of said plurality of data accesses being independently addressable, said cache comprising:

• a single-ported interleaved storage array comprising a plurality of banks of single-ported memory cells, each of said cells being independently addressable;
• access control logic coupled to the storage array, wherein the access control logic determines whether data stored in locations requested by the plurality of accesses are contained in the storage array using tag matching;
• bank selection means coupled to said storage array and responsive to the addresses requested by said plurality of data accesses, said selection means for accessing a plurality of banks in said storage array per clock cycle according to said addresses;
• contention logic coupled to said bank selection means for prioritizing said plurality of data accesses, such that when the plurality of data accesses are to the same bank of said storage array, said contention logic prioritizes said plurality of data accesses in order to complete said plurality of data accesses;
• a plurality of data ports, each of said plurality of data ports stored in locations requested by one of said plurality of execution units for transferring data between said storage array and said plurality of execution units;
• and
• control means for controlling the transfer of data between said storage array and said plurality of data ports, wherein the control means directs data corresponding to the plurality of data accesses from said storage array to the plurality of execution units using said plurality of data ports, such that the plurality of accesses occur in one clock cycle.

A microprocessor formed in a single integrated circuit chip for use in a computer system, said microprocessor comprising:

• an instruction decoder for receiving and decoding a plurality of instructions to produce a plurality of decoded instructions;
• a cache memory for storing data;
• a plurality of execution units coupled to said instructions decoder and said cache memory for executing said plurality of decoded instructions, wherein at least two of the plurality of execution units execute a first instruction in said plurality of instructions and a second instruction in said plurality of instructions respectively using a first data access and a second data access to the cache memory respectively, where the first data access includes a first address and the second data access includes a second address;
• wherein the cache memory includes
• a single-ported interleaved storage array having a plurality of banks of single-ported memory cells, wherein each of said cells is independently addressable, wherein the storage array is arranged as a plurality of cache lines, such that each of said plurality of banks includes a predetermined number of bytes of each of said plurality of cache lines,
• decoding logic coupled to receive the first address for the first data access and the second address for the second data access, wherein the decoding logic decodes the first address and the second address to produce a first set address and a second set address respectively,
• a bank selection mechanism coupled to receive the first set address and the second set address, and wherein the bank selection mechanism accesses a first bank in said plurality of banks and a second bank in said plurality of banks in parallel during a single clock cycle in response to the first set address and the second set address respectively,
• a data path coupled to said storage array and the plurality of execution units for transferring data between said storage array and said plurality of execution units in response to said plurality of data accesses, such that a plurality of data accesses occur in said cache memory per clock cycle.

A computer system comprising:

• bus means for transferring data;
• memory means for storing data, wherein the memory means is coupled to the bus means;
• a processor formed in a single integrated circuit chip for use in a computer system, wherein said processor is coupled to said bus means for executing a plurality of instructions, said processor including:
• an instruction decoder for receiving and decoding the plurality of instructions to produce a plurality of decoded instructions;
• a cache memory for storing data;
• a plurality of execution units coupled to said instructions decoder and said cache memory for executing said plurality of decoded instructions, wherein at least two of the plurality of execution units execute a first instruction in said plurality of instructions and a second instruction in said plurality of instructions respectively using a first data access and a second data access to the cache memory respectively, where the first data access includes a first address and the second data access includes a second address;
• wherein the cache memory includes
• a single-ported interleaved storage array having a plurality of banks of single-ported memory cells for storing a plurality of cache lines, wherein each of said cells is independently addressable, wherein a portion of each of the plurality of cache lines is stored in each of the plurality of banks;
• cache management logic coupled to receive the first address and the second address for determining if data corresponding to the first address and the second address is contained in said storage array, such that the memory means is accessed for said data corresponding to said first address if data corresponding to the first address is not contained in the storage array and the memory means is accessed for said data corresponding to said second address if data corresponding to the second address is not contained in the storage array,
• decoding logic coupled to receive the first address for the first data access and the second address for the second data access, wherein the decoding logic decodes the first address and the second address to produce a first set address and a second set address respectively,
• a bank selection mechanism coupled to receive the first set address and the second set address, and wherein the bank selection mechanism accesses a first bank in said plurality of banks and a second bank in said plurality of banks during a single clock cycle in response to the first set address and the second set address respectively,
• a data path coupled to said storage array and the plurality of execution units for transferring data between said storage array and said plurality of execution units in response to said plurality of data accesses, such that a plurality of data accesses occur in said cache memory per clock cycle.