US 5,559,502 A · Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses

Abstract

Two-wire bus system comprises a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses. A communication bus system has a single clock wire and a single data wire. Each wire has wired logic that upon presentation of any prevalence logic signal value imparts to that wire the prevalence logic value regardless of any non-prevalence value second presented thereto. The system has clock synchronization by a master station of any information transmission. The system arbitrates among coexistent prospective masters to select a single actual master. The protocol has a start condition by presenting said first value to the data wire with the clock line at the second value, and generates any subsequent data wire transition exclusively under existence of the prevalence value on the clock wire. The subsequent stop condition is represented by a transition to the second value on the data wire with the clock wire at the second value. The message format has an initial byte accommodating either a short slave address, or alternatively both a control signal indicating a long-format slave address inclusive of a high significance address part, to be followed in the next byte by a low significance part of the address. For enhancing the bit rate, the system has a switched pull up device, whereas furthermore each station has a slope controlled output stage.

Claims20

Dependent claims

A communication bus system having an extended addressability feature, comprising:

a single clock wire and a single data wire each including logic means for enabling said wires to each assume a particular second voltage value and to enable each wire to be forced to a first voltage value;
a plurality of stations interconnected by said clock wire and said data wire, wherein at least one of said stations includes means for forcing each of said wires to their respective first voltage values and means for allowing each of said wires to assume their respective second voltage values, and wherein a master station is one of said stations which has gained priority to said data wire for initiating transfer of information on said data wire, said system being arranged for transferring information between said stations on said data wire under the synchronization of the voltage levels of said clock wire, and wherein each of said stations is addressable by one of (i) a long-format slave address and (ii) a short-format slave address;
arbitration means for selecting one of said stations as a master station upon more than one of said stations attempting to provide information on said data wire at the same time;
said master station having protocol means for generating information on said data wire in synchronization with the voltage level of said clock wire, said master station further including message formatting means for enabling said master station to produce in an initial byte of information one of
a) a short-format address and
b)(i) a control signal indicating a forthcoming long-format address and (ii) a first significant portion of the long-format address, and
if the control signal is present in the initial byte of data then in a second byte of data said message formatting means producing a second significant portion of the long-format address such that said master station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in said system.

4 more elements

A master station for use in a communication bus system having an extended addressability feature and a plurality of stations, each station having one of i) a long-format address, and ii) a short-format address, said master station comprising:

means for connecting to a single clock wire and a single data wire, each wire including logic means for enabling said wires to each assume a particular second voltage value and to enable each wire to be forced to a first voltage value;
means for providing clock synchronization signals on said clock wire for synchronizing information transmission between said stations;
information bit means for providing information on said data wire by forcing said data wire to its respective first voltage value and for allowing said data wire to assume its respective second voltage value;
detecting means for detecting bitwise data inconsistency between the voltage value of said data wire and the expected voltage value of said data wire which corresponds to the information provided by said information bit means;
and
message formatting means for producing in an initial byte of information one of
a) a short-format address and
b) (i) a control signal indicating a forthcoming long-format address and (ii) a first significant portion of the long-format address, and
if the control signal is present in the initial byte of data, then in a second byte of data said message formatting means producing a second significant portion of the long-format address such that said master station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in said system.

6 more elements

A slave station for use in a communication bus system having an extended addressability feature, comprising:

means for attaching to a single clock wire and a single data wire wherein each wire includes logic means for enabling said wires to each assume a particular second voltage value and to enable each wire to be forced to a first voltage value;
means for receiving clock synchronization signals for synchronization;
said communication bus system including
a) a plurality of stations interconnected by said clock wire and said data wire, wherein at least one of said stations includes means for forcing each of said wires to their respective first voltage values and means for allowing each of said wires to assume their respective second voltage values, and wherein a master station is one of said stations which has gained priority to said data wire for initiating transfer of information on said data wire, said system being arranged for transferring information between said stations on said data wire under the synchronization of said voltage levels of said clock wire, and wherein each of said stations is addressable by one of (i) a long-format address and (ii) a short-format address;
and
b) arbitration means for selecting one of said stations as a master station upon more than one of said stations attempting to provide information on said data wire at the same time;
said master station having protocol means for generating information on said data wire in synchronization with the voltage level of the clock wire, said master station further including message formatting means for enabling said master station to produce in an initial byte of information one of
a) a short-format address and
b)(i) a control signal of a forthcoming long-format address and (ii) a first significant portion of the long-format address, and
if the control signal is present in the initial byte of data then in a second byte of data said message formatting means producing a second significant portion of the long-format address such that said master station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in said system.

7 more elements

A system for data transmission comprising:

(A) slave stations comprising a data terminal and a clock terminal and each slave station being addressable by one of i) a long-format address and ii) a short-format address
(B) at least one master transmitting station which is capable of controlling data transmission, comprising:
(a) a clock terminal;
(b) a data terminal;
(c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;
(d) means for producing a start signal which indicates that the master station is prepared to control data transmission by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;
(e) means for producing a stop signal which indicates that the master station has finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;
(f) at least all but one of the master transmitting stations further comprising means for establishing priority when a plurality of master stations simultaneously attempt to control data transmission;
and
(g) at least one master transmitting station including message formatting means for producing in an initial byte of data one of a) a short-format address and b) (i) a control signal indicating a forthcoming long-format address and (ii) a first significant portion of the long-format address, and if the control signal is present in the initial byte of data then in a second byte of data the message formatting means producing a second significant portion of the long-format address such that the master transmitting station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in the system;
(C) a data bus which interconnects the data terminals of all the stations;
(D) a clock bus which interconnects the clock terminals of all the stations;
and
(E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

11 more elements

A system for data transmission comprising:

(A) slave stations comprising a data terminal and a clock terminal and each slave station addressable by one of i) a short-format address and ii) a long-format address;
(B) at least two master transmitting stations which are capable of controlling data transmission, comprising each:
(a) a clock terminal;
(b) a data terminal;
(c) means for producing a clock signal at the clock terminal by allowing the clock terminal to assume a second voltage level for each of a series of periodic clock pulse intervals and by forcing the clock terminal to a first voltage level at all other times during production of the clock signal;
(d) means for producing a start signal which indicates that the master station is prepared to control data transmission by allowing the voltage level at the data terminal to assume a second voltage level for a first fraction of a clock pulse interval and by then forcing the voltage at the data terminal to a first voltage level during the same clock pulse interval;
(e) means for producing a stop signal which indicates that the master station has finished controlling data transmission by forcing the voltage level at the data terminal to the first voltage level during a first fraction of a clock pulse interval and then allowing the voltage at the data terminal to transition to the second voltage level during the same clock pulse interval;
and
(f) message formatting means for producing in an initial byte of data one of a) a short-format address and b) (i) a control signal indicating a forthcoming long-format address and (ii) a first significant portion of the long-format address, and if the control signal is present in the initial byte of data then in a second byte of data the message formatting means producing a second significant portion of the long-format address such that said master station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in said system;
(C) a data bus which interconnects the data terminals of all the stations;
(D) a clock bus which interconnects the clock terminals of all the stations;
and
(E) means which maintain the buses at the second voltage level in the absence of forcing by the stations.

10 more elements

A method of data transmission on a data transmission system which comprises a plurality of stations, each station having a data terminal and a clock terminal and addressable by one of i) a short-format address and ii) a long-format address, the data terminals of all stations being interconnected by a data bus and the clock terminals of all stations being interconnected by a clock bus, comprising:

transmitting a clock signal from a first master station along the clock bus by allowing the clock terminal of the first master station to assume a second voltage level during each of a series of periodic clock pulse intervals and by forcing the clock terminal of the first master station to a first voltage level at all other times during transmission of the clock signal;
transmitting a start signal, which indicates that the first master station is prepared to control data transmission, by allowing the data terminal of the first master station to assume a second voltage level during a first fraction of a clock pulse interval and then forcing the voltage level at the data terminal of the first master station to a first voltage level during said clock pulse interval;
transmitting a stop signal which indicates that the first master station has finished controlling data transmission by forcing the voltage level at the data terminal of the first master station to the first voltage level during a first fraction of the clock pulse interval and by then allowing the voltage level at the data terminal of the first master station to transition to the second voltage level during the same clock pulse interval;
and
message formatting means for producing in an initial byte of data one of a) a short-format address and b) (i) a control signal indicating a forthcoming long-format address and (ii) a first significant portion of said long-format address, and if the control signal is present in the initial byte of data then in a second byte of data said message formatting means producing a second significant portion of the long-format address such that the first master station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in the system.

2 more elements

A communication system comprising:

a first plurality of transmitting and receiving stations including at least one master station and at least one slave station addressable by one of i) a short-format address and ii) a long-format address;
a data bus for transporting a series of data bits between at least one transmitting station and at least one receiving station;
a clock bus for transporting a synchronizing clock signal in synchronism with each data bit;
each bus further comprising logic means for forming a wired logic function between levels which denote a first and a second logic value respectively which are transmitted by the stations so that the level of the bus can be pulled to the first logic value by any station presenting a signal having the first logic value to the bus thereby masking any signal having the second logic value that may be presented to the bus;
wherein each master station comprises:
(a) clock transmitting means which generate a series of clock pulses, each having the second logic value, on the clock bus to define a series of bit cells;
(b) means which form a first stop signal by forming a signal transition on the data bus from said first logic value to said second logic value, during the presence of a signal of the second logic value on the clock bus;
(c) means which form a first start signal by forming a signal transition on the data bus from said second logic value to said first logic value during the presence of a signal of the second logic value on the clock bus;
(d) message formatting means for producing in an initial byte of data one of a) a short-format address and b) (i) a control signal indicating a forthcoming long-format address and (ii) a first significant portion of the long-format address, and if the control signal is present in the initial byte of data then in a second byte of data said message formatting means producing a second significant portion of the long-format address such that the master station does not address a station having a short-format address when addressing a station having a long-format address thereby enabling stations having both short-format and long-format addresses to communicate in the system.

6 more elements

Dependencies are inferred from the claim text.

Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses

Life of this patent

Two-wire bus system comprising a clock wire and a data wire for interconnecting a number of stations and allowing both long-format and short-format slave addresses

Life of this patent

Abstract

Claims20