# US 5,557,148 A · Hermetically sealed semiconductor device > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 5,557,148 A - Document ID: US5557148A - Status: Granted - Kind: A - Application number: 08/359,944 - Filed: 1994-12-20 - Granted: 1996-09-17 - Earliest claimed: 1993-03-30 - Assignees: Tribotech - Inventors: Earl S. Cain - Web page: https://patentgrep.com/patent/US5557148A ## CPC - H10W 74/141: {the encapsulations being on at least the sidewalls of the semiconductor body} - H10W 72/5522: {comprising gold [Au]} - H10W 72/59: Bond pads specially adapted therefor - H10W 72/90: Bond pads, in general - H10W 72/923: {Bond pads having multiple stacked layers} - H10W 72/952: {comprising metals or metalloids, e.g. PbSn, Ag or Cu} - H10W: GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10 ## Abstract A semiconductor device which includes device bonding pads exposed through oxide windows formed in a passivation oxide layer providing electrical connections to the metallized regions, a bonding pad of a different material electrically connected to the device bonding pad through a barrier layer, and a protective layer overlying the edges of said passivation oxide layer in contact with the device to seal the edges of the protective layer and a seal formed at said windows whereby the device is protected against the environment without the necessity of a separate metal or ceramic housing. ## Claims ### Claim 1 A semiconductor device which includes a semiconductor body having an upper surface, a lower surface and side surfaces extending between said upper and lower surfaces, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bonding pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges spaced from said bonding pad areas, the improvement comprising a metal layer of a metal which acts as a barrier against migration of corrosion resistant metal formed on and covering said bonding pad areas, a protective layer extending over said outer edges of said insulating and oxide layers and in contact with said semiconductor body to seal said outer edges of said insulating and oxide layers and environmentally protect said device, said protective layer having inner edges defining windows at said bonding pad areas, a corrosion resistant metal layer formed on said metal layer for connecting to said bonding pad areas through said metal layer and for sealing said inner edges of said protective layer, and a bottom protective layer, said protective layer extending over said side surfaces of said semiconductor body to merge with the bottom protective layer to cocoon said device. ### Claim 2 (depends on 1) A semiconductor device as in claim 1 in which the corrosion resistant metal layer is gold. ### Claim 3 (depends on 2) A semiconductor device as in claim 2 in which said metal layer, protective layer and gold layer are multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the protective layers. ### Claim 4 (depends on 1, 2, 3) A semiconductor device as in claims 1, 2 or 3 in which said metal layer extends over said inner edges of said oxide layer and said protective layer is an insulating layer. ### Claim 5 (depends on 1, 2, 3) A semiconductor device as in claims 1, 2 or 3 in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a silicon oxide layer. ### Claim 6 (depends on 1, 2) A semiconductor device as in claims 1 or 2 in which said protective layer is a metal protective layer. ### Claim 7 (depends on 1) A semiconductor device as in claim 1 in which said protective layer comprises a metal protective layer and a silicon oxide layer and in which said corrosion resistant metal layer extends over said inner edges of at least one of the metal protective layer and the silicon oxide layer. ### Claim 8 (depends on 7) A semiconductor device as in claim 7 in which said metal layer, metal protective layer, corrosion resistant metal layer and silicon oxide layer comprise multiple layers to provide pinhole coverage and in which at least one of the corrosion resistant metal layers extends over said inner edges of at least one of the metal protective layers and silicon oxide layers. ### Claim 9 A semiconductor device which includes a semiconductor body having upper and lower surfaces and side surfaces extending between said upper and lower surfaces, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bonding pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges spaced from said bonding pad areas, the improvement comprising aluminum bonding pads on said metallization at said bonding pad areas, a layer of a metal which acts as a barrier against migration of gold formed on and covering said aluminum bonding pads, a protective layer having inner edges defining windows at said bonding pad areas, said protective layer extending over said outer edges of said insulating and oxide layers and contacting said semiconductor body to seal said outer edges of said insulating and oxide layers and environmentally protect said, device, sealing means for sealing said inner edges of said oxide layer to environmentally protect said device, a gold layer formed on said metal layer for connecting to said bonding pads through said metal layer, and a bottom protective layer, said protective layer extending over said side surfaces of said semiconductor body to merge with said bottom protective layer to cocoon the device. ### Claim 10 (depends on 9) A semiconductor device as in claim 9 in which said metal layer, protective layer and gold layer are multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the protective layers. ### Claim 11 (depends on 9, 10) A semiconductor device as in claims 9 or 10 in which said metal layer has outer edges spaced from said bond pad area and in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a dielectric insulating layer which extends over said outer edges of said metal layer to provide, in combination, said sealing means. ### Claim 12 (depends on 9, 10) A semiconductor device as in claims 9 or 10 in which said metal layer has outer edges spaced from said bond pad area and in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a silicon oxide layer which extends over said outer edges of said metal layer to provide, in combination, said sealing means. ### Claim 13 (depends on 9) A semiconductor device as in claim 9 in which said protective layer is a metal protective layer and said sealing means comprises an insulating layer which extends over said inner edges of said oxide layer and said inner edges of the metal protective layer. ### Claim 14 (depends on 9) A semiconductor device as in claim 9 in which said protective layer comprises a metal protective layer and a silicon oxide layer and in which said gold layer extends over said inner edges of at least one of the metal protective layer and the silicon oxide layer. ### Claim 15 (depends on 14) A semiconductor device as in claim 14 in which said metal layer, metal protective layer, gold layer and silicon oxide layer comprise multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the metal protective layers and silicon oxide layers. ### Claim 16 A semiconductor device which includes a semiconductor body having upper and lower surfaces and side surfaces extending between said upper and lower surfaces, said semiconductor body having circuit metallization carried by one or more insulating layers for connection to active regions of said device, and an oxide layer having inner edges defining windows overlying said circuit metallization to expose bond pad areas of said metallization for connection to said active regions, said oxide layer and said insulating layers having outer edges spaced from said bond pad areas, the improvement comprising a first metal layer of a metal which acts as a barrier against migration of gold formed on and covering said bond pad areas, a protective layer extending over said outer edges of said insulating and oxide layers and in contact with the semiconductor body to seal said outer edges of said insulating and oxide layers and environmentally protect said device, said protective layer having inner edges defining windows at said bond pad areas, a gold layer formed on said first metal layer for connecting to said bond pad areas through said metal layer and for sealing said inner edges of said protective layer, a second metal layer which acts as a barrier against migration of solder covering said gold layer, a solder bond pad formed on said second metal layer, and a bottom protective layer, said protective layer extending over said surfaces of said semiconductor body to merge with the bottom protective layer to cocoon the device. ### Claim 17 (depends on 16) A semiconductor device as in claim 16 in which said first metal layer, protective layer and gold layer are multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the protective layers. ### Claim 18 (depends on 16, 17) A semiconductor device as in claims 16 or 17 in which said metal layer extends over said inner edges of said oxide layer and said protective layer is an insulating layer. ### Claim 19 (depends on 16, 17) A semiconductor device as in claims 16 or 17 in which said metal layer extends over said inner edges of said oxide layer and said protective layer is a silicon oxide layer. ### Claim 20 (depends on 16) A semiconductor device as in claims 16 in which said protective layer is a metal protective layer. ### Claim 21 (depends on 16) A semiconductor device as in claim 16 in which said protective layer comprises a metal protective layer and a silicon oxide layer and in which said gold layer extends over said inner edges of at least one of the protective metal layer and the silicon oxide layer. ### Claim 22 (depends on 21) A semiconductor device as in claim 21 in which said first and second metal layers, metal protective layer, gold layer and silicon oxide layer comprise multiple layers to provide pinhole coverage and in which at least one of the gold layers extends over said inner edges of at least one of the metal protective layers and silicon oxide layers. ### Claim 23 (depends on 1, 9, 16) A semiconductor device as in claims 1, 9 or 16 in which said protective layer comprises a metal protective layer and a silicon oxide layer extending over said side surfaces of said semiconductor body to merge with the bottom protective layer.