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US 5,555,510 AGranted
Automatic computer card insertion and removal algorithm
AssigneeIntel Corporation
InventorsJerry Verseput, Fong-Shek Lam, Prasanna Shah
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AssigneeIntel Corporation
InventorsJerry Verseput, Fong-Shek Lam, Prasanna Shah
Estimating the term…
A method applicable to a host computer system having a system bus connected to a CPU, and a PCMCIA controller having status registers, means for supplying back off signals to the CPU and line buffers capable of being in a normal and high impedance state. A multi pin connector is located in each card socket and connected to a line buffer. Each connector has common address, data and control pins, power pins, ground pins longer than the data pins and card detect signal pins shorter than the signal pins. The first step is to detect the commencement of an insertion or removal of a PCMCIA card to or from a socket by monitoring the ground and card detect signal pins. After detection, commence termination of all CPU usage of common address, data and control lines by asserting a back off signal. Next, determine if the usage is terminated by monitoring the status registers in the controller. Next, place the common address, data and control lines in a high impedance state. Next, detect that the PC card has been completely inserted or removed by monitoring the ground pins or the card detect signal pins. Next, apply power to the PCMCIA card socket. After a delay return the common address, data and control lines to their normal operating impedance level.
In a method of operating a host computer system having at least a system bus which is connected to a CPU, a system memory and a controller having status registers and means for supplying back off signals indicating that new tasks cannot be accepted to the CPU and a plurality of line buffers capable of being in a normal and high impedance state, and a plurality of add in PC card sockets for receiving PC cards connected to said controller, said sockets each having a multi pin connector that includes common address, data and control lines as well as power, ground and card detect signal pins connected to said line buffers, the steps comprising:
In a method of operating a host computer system having at least a system bus which is connected to a CPU, a system memory and a controller having status registers and means for supplying back off signals indicating that new tasks cannot be accepted to the CPU and a plurality of line buffers capable of being in a normal and high impedance state, and a plurality of add in PC card sockets for receiving PC cards connected to said controller, said sockets each having a multi pin connector that includes common address, data and control lines as well as power, ground and card detect signal pins connected to said line buffers, the steps comprising:
In a method of operating a host computer system having at least a system bus which is connected to a CPU and system memory and having a plurality of add in PC card sockets for receiving PC cards, said sockets being connected by common address, data and control lines through a controller to said system bus, and wherein each socket has a first state in which a PC card is fully inserted and a second state in which a PC card is fully disengaged, the steps comprising:
Dependencies are inferred from the claim text.