US 5,555,383 AGranted

Peripheral component interconnect bus system having latency and shadow timers

AssigneeInternational Business Machines Corporation

InventorsUri Elazar, Yehuda Peled

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Abstract

A PCI system is provided with a shadow register and a shadow timer. When a master device sends an address designating a target device that is connected to another bus, the device's latency value is recorded in the shadow register. While the PCI-PCI bridge arbitrates for the target bus, the master's latency timer increments but the shadow timer will not begin to increment until the PCI-PCI bridge receives a grant# from the target's bus and data transmission begins. Accordingly, the bus arbiter will not de-assert the grant# until the shadow timer has reached the latency value or the master device has released the bus after completing its data transmission. This ensures that the master device will be allocated a time period equal to its latency value to transmit data.

Claims19

Dependent claims

A computer system, comprising:

a central processing unit;
a bridge unit coupled to said central processing unit;
at least one shadow timer for counting a received time value;
first and second buses, each of which is coupled to said bridge unit;
a plurality of first peripheral units coupled to said first bus, each of said plurality of first peripheral units including an associated latency timer for counting an associated latency time value;
and
a plurality of second peripheral units coupled to said second bus, each of said plurality of second peripheral units also including an associated latency timer for counting an associated latency time value, the latency time value associated with each of said first and second peripheral units representing a time necessary to perform a transfer operation;
wherein each of said first peripheral units is operable for transferring and receiving information from any one of the other first peripheral units and from any one of said second peripheral units;
and
wherein during a transfer operation in which information from one of said first peripheral units is transferred to one of said second peripheral units, the one first peripheral unit receives control of said first bus, the latency timer associated with the one first peripheral unit begins its counting operation with its associated latency time value in response to the one first peripheral unit obtaining control of said first bus, said at least one shadow timer receives the latency time value associated with the one first peripheral unit, and said at least one shadow timer begins its counting operation with said received latency time value in response to the one first peripheral unit obtaining control of said second bus and starting the transfer of information to the one second peripheral unit.

7 more elements

Dependencies are inferred from the claim text.