Non-volatile semiconductor memory device

A non-volatile semiconductor memory device comprising:

• semiconductor substrate;
• a memory cell array constituted by memory cells capable of electrically rewriting data and arranged in the form of a matrix, each of said memory cells being formed by stacking a charge storage layer and a control gate on said semiconductor substrate;
• threshold voltage changing means for applying a threshold voltage changing write pulse between said control gate and said semiconductor substrate to change the threshold voltage of each of an arbitrary number of memory cells in said memory cell array;
• threshold voltage verify means for detecting the states of said arbitrary number of memory cells after application of the threshold voltage changing write pulse;
• threshold voltage re-changing means for applying a threshold voltage changing write pulse to a memory cell, of said arbitrary number of memory cells, whose threshold voltage has not reached a desired threshold voltage yet, for a time a, thereby changing the threshold voltage again;
• and
• repeating means for, after a threshold voltage changing operation and a threshold voltage verify operation are respectively performed by said threshold voltage changing means and said threshold voltage verify means, repeating a threshold voltage re-changing operation by said threshold voltage re-changing means and the threshold voltage verify operation until the threshold voltage of said memory cell reaches the desired value,
• wherein said threshold voltage re-changing means includes means for increasing a potential of the threshold voltage changing write pulse by a pulse peak value increase .DELTA.V.sub.PP every time a threshold voltage re-changing operation is performed, and
• said repeating means includes means for electrically erasing or writing data such that the width of the threshold voltage distribution of said memory cells whose threshold voltages have reached the desired threshold voltage becomes equal to .DELTA.V.sub.PP.

A non-volatile semiconductor memory device comprising:

• a memory cell array constituted by memory cells capable of electrically rewriting data and arranged in the form of a matrix, each of said memory cells being formed by stacking a charge storage layer and a control gate on a semiconductor layer;
• erase means for performing an erase operation to set data in each memory cell of said memory cell array to "0";
• pulse applying means for applying threshold voltage changing write pulses (V.sub.pp1, V.sub.pp2 . . . , V.sub.ppn) corresponding to write data ("1", "2", . . . , "n") between said control gate and said semiconductor layer to change the threshold voltage of each of an arbitrary number of memory cells in said memory cell array;
• threshold voltage verify means for detecting the states of said arbitrary number of memory cells upon application of the threshold voltage changing write pulses;
• rewrite pulse applying means for applying threshold voltage changing write pulses corresponding to the write data to memory cells, of said arbitrary number of memory cells, whose threshold voltage values have not reached desired threshold voltages (V.sub.th1, V.sub.tH2, . . . , V.sub.thn) corresponding to the write data ("1", "2",. . . , "n"), thereby changing the threshold voltages again in accordance with the write data;
• and
• repeating means for, after a threshold voltage changing operation and a threshold voltage verify operation are respectively performed by said write pulse applying means and said threshold voltage verify means, repeating a threshold voltage re-changing operation by said rewrite pulse applying means and the threshold voltage verify operation until the threshold voltages of said memory cells reach the desired values corresponding to the write data,
• wherein said write pulse applying means includes means for setting the threshold voltage changing write pulses according to V.sub.pp1 =V.sub.pp2 -.DELTA.V.sub.ppd2 =V.sub.pp3 -.DELTA.V.sub.ppd3 =. . . V.sub.ppn -.DELTA.V.sub.ppdn, and
• said rewrite pulse applying means includes means for setting the desired threshold voltages according to Vt.sub.thi -V.sub.thi-1 =.DELTA.V.sub.ppdi (i=2, 3, . . . , n).

A non-volatile semiconductor memory device comprising:

• a semiconductor substrate;
• a plurality of memory cells, each including source and drain regions formed in a surface region of said semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate sequentially stacked on said semiconductor substrate, said memory cells being capable of electrically rewriting data by exchanging charges and being arranged in the form of a matrix;
• and
• means for applying a high potential to said semiconductor substrate and said control gate of each non-selected memory cell and applying an intermediate potential to said control gate of a selected memory cell in a first data erase operation, and applying a high potential to said semiconductor substrate and said control gate of each non-selected memory cell and applying a potential lower than the intermediate potential to said control gate of said selected memory cell in second and subsequent data erase operations, thereby removing electrons from said charge storage layer.

A non-volatile semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells, which are arranged in a matrix, capable of electrically rewriting and erasing data, said memory cell having a source and a drain;
• a plurality of bit lines coupled to said drain of said memory cells;
• a plurality of word lines which are control gates of said memory cells;
• writing means for sequentially increasing a potential difference between a word line and at least one of a substrate, a source and a drain during a page write operation;
• means for reading information written by said writing means and for rewriting memory cells which are insufficiently written;
• and
• means for preventing to rewrite a memory cell in which the write operation is completed by reducing a potential difference between said word line and at least one of said substrate, said source and said drain, whereby
• the write operation is performed in an optimal condition for each memory cell.