US 5,554,552 A · PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof

Abstract

Multi-state EEPROM and Flash EPROM devices with charge control are formed with a P-N junction floating gate with an N type capacitor on top of the channel area and a P type capacitor on top of the field oxide area. An additional mask and a P+/N+ implant instead of POCl.sub.3 doping are required to fabricate this device. The threshold voltage of this device is well controlled by the ratio of C.sub.fp, capacitance of the P type capacitor and C.sub.fn capacitance of the N type capacitor. The coupling ratio "READ" and "WRITE" are exactly the same as current N type floating gate. The "ERASE" efficiency is improved by 1.5 volt higher voltage to the drain electrode of the EEPROM or the source electrode of a flash EPROM. Also, a good P-N junction floating gate, with reverse junction leakage less than 10 pA for 7 Volt reverse bias, is required to discharge the N type capacitor without affecting the P type capacitor.

Claims20

Dependent claims

A method of forming a floating gate ROM device comprising

providing a lightly doped P- semiconductor substrate,
forming a doped source region and a doped drain region in the substrate,
forming a tunnel oxide layer and field oxide regions formed over the surface of the substrate,
forming a PN junction floating gate electrode from a first polysilicon layer comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region,
forming an intergate electrode dielectric layer covering the PN floating gate electrode,
forming a polysilicon control gate electrode from a second polysilicon layer over the intergate electrode dielectric layer, and
forming an additional dielectric layer over the control gate electrode.

4 more elements

A method of forming a floating gate ROM device comprising

forming a lightly doped P- semiconductor substrate,
forming a doped source region and a doped drain region in the substrate,
forming a tunnel oxide layer and field oxide regions over the surface of the substrate, a PN junction floating gate electrode comprising doped polysilicon with an N doped region above the tunnel oxide layer and at least one P doped region above the field oxide region juxtaposed with the N doped region,
forming an interpolysilicon ONO dielectric layer covering the PN floating gate electrode,
forming a polysilicon control gate electrode over the ONO dielectric layer,
forming an additional dielectric layer over the control gate electrode with a via opening down to the drain region, and
forming an electrical conductor over the additional dielectric layer extending down into the via opening into contact with the drain region.

4 more elements

Dependencies are inferred from the claim text.

PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof

Life of this patent

PN junction floating gate EEPROM, flash EPROM device and method of manufacture thereof

Life of this patent

Abstract

Claims20