US 5,553,020 A · Structure and method for low current programming of flash EEPROMs

Abstract

A system and method for programming non-volatile memory enables fast low current programming. Low current programming is achieved by applying a source bias voltage and increasing the drain voltage to be greater than the source bias voltage to maintain fast programming. Furthermore, the control gate voltage may be stepped or ramped from a minimum value to a maximum value to further reduce the peak channel current and to allow the flash cell threshold voltage to be placed to an exact value, for MLC applications. Ramping or stepping of the control gate may be done independently or in conjunction with an applied source bias voltage. Furthermore, the reduced cell current allows more cells to be programmed in parallel which improves program performance and the drain select device can be reduced in size to reduce die area.

Claims8

Dependent claims

A system comprising:

a processor;
and
a memory coupled to the processor, said memory comprising:
a memory array comprising a plurality of cells, each cell comprising a floating gate, control gate, source junction and drain junction;
and
programming circuitry for programming a cell by applying an initial gate voltage to the control gate of the cell, and stepping the control gate voltage in predetermined increments to a maximum gate voltage, applying a source bias voltage to the source junction of the cell, and applying a drain voltage pulse to the drain junction of the cell to cause hot electron injection of electrons onto the floating gate, said drain voltage pulse applied at each stepped increment of the control gate voltage;
said processor issuing control signals to the programming circuitry to program the cell.

4 more elements

Dependencies are inferred from the claim text.

Structure and method for low current programming of flash EEPROMs

Life of this patent

Structure and method for low current programming of flash EEPROMs

Life of this patent

Abstract

Claims8