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US 5,550,870 AGranted
Viterbi processor
AssigneeLucent Technologies Inc.
InventorsDavid M. Blaker, Gregory S. Ellard, Mohammad S. Mobin
Life of this patent
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Abstract
A digital signal processor with an embedded error correcting coprocessor (ECCP) is disclosed. The ECCP provides soft symbol Viterbi decoded outputs which have the absolute value of the accumulated cost difference of competing states concatenated with the traceback bit or most significant bit of the next state.
Claims7
A method of trellis decoding comprising:
- determining a set of two or more branch metric components, X1 and XQ;
- determining if any of said branch metric components X1, XQ of said set exceeds a predetermined saturation value;
- setting any branch metric component of said set which exceeds said predetermined value to said predetermined saturation value.
A method of trellis decoding comprising:
- determining two or more branch metric values associated with state transitions in a Viterbi trellis;
- said branch metric values having a maximum of n bits;
- forming a k bit number associated with each of said branch metric value by:
- if k<n, discarding the n-k least significant bits;
- if k>n, shifting each of said branch metric bits so that their most significant bits is the k th bit position and concentrating zeros in the least significant bit positions, thereby obtaining two to more modified branch metrics, each having k bits.
2 more elements
Dependencies are inferred from the claim text.